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Linear phase frequency detector and charge pump for phase-locked loop

A phase frequency and detector technology, applied in the field of circuits, can solve problems such as performance degradation

Active Publication Date: 2009-09-23
QUALCOMM INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Charge pump nonlinearity due to current mismatch can cause additional phase noise that can degrade performance

Method used

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  • Linear phase frequency detector and charge pump for phase-locked loop
  • Linear phase frequency detector and charge pump for phase-locked loop
  • Linear phase frequency detector and charge pump for phase-locked loop

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Embodiment Construction

[0019] The techniques described herein may be used in various types of circuits such as integer-N PLLs, fractional-N PLLs, multi-modulus dividers (MMDs), sigma-delta (sigma-delta) frequency synthesizers, and the like. An integer-N PLL divides the frequency of the oscillator signal from the VCO by an integer divider ratio N, where N≧1. A fractional-N PLL divides the frequency of the oscillator signal by a non-integer divider ratio R (eg, sometimes by N and other times by N+1), where N<R<N+1. A sigma-delta frequency synthesizer utilizes a sigma-delta modulator to generate a non-integer divider ratio R for a fractional-N PLL.

[0020] figure 1 A block diagram of a design of a sigma-delta frequency synthesizer 100 with a fractional-N PLL 110 and a sigma-delta modulator 170 is shown. PLL 110 includes phase frequency detector 120 , charge pump 130 , loop filter 140 , voltage controlled oscillator (VCO) 150 and divider 160 .

[0021] The phase frequency detector 120 learns from th...

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Abstract

Techniques for achieving linear operation for a phase frequency detector and a charge pump in a phase-locked loop (PLL) are described. The phase frequency detector receives a reference signal and a clock signal, generates first and second signals based on the reference and clock signals, and resets the first and second signals based on only the first signal. The first and second signals may be up and down signals, respectively, or may be down and up signals, respectively. The phase frequency detector may delay the first signal by a predetermined amount, generate a reset signal based on the delayed first signal and the second signal, and reset the first and second signals with the reset signal. The charge pump receives the first and second signals and generates an output signal indicative of phase error between the reference and clock signals.

Description

technical field [0001] The present invention relates generally to circuits, and more particularly to phase locked loops. Background technique [0002] Phase-locked loops (PLLs) are commonly used in many electronic circuits and are especially important in communication circuits. For example, digital systems use clock signals to trigger synchronous circuits (eg, flip-flops). The transmitter system and the receiver system use a local oscillator (LO) signal for frequency up-conversion and frequency down-conversion, respectively. A wireless device, such as a cellular telephone, in a wireless communication system typically uses a clock signal for digital circuits and an LO signal for transmitter and receiver circuits. The clock signal and the LO signal are often generated with a voltage controlled oscillator (VCO) operating within the PLL. [0003] A PLL typically includes a phase-frequency detector, charge pump, loop filter, and VCO. The phase frequency detector, charge pump,...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03L7/00
CPCH03L7/1976H03L7/0891H03L7/089H03L7/093
Inventor 张刚
Owner QUALCOMM INC