Shift register and grid driving device for liquid crystal display

Abstract

The invention relates to a shift register and a grid driving device for a liquid crystal display. The shift register comprises a first thin film transistor, a second thin film transistor, a third thin film transistor and a fourth thin film transistor and further comprises a pull-down thin film transistor driving unit and a pull-down thin film transistor, wherein the pull-down thin film transistor driving unit is used for controlling the turn-on of the pull-down thin film transistor when a signal output terminal outputs low level and the signal input by a first clock signal input terminal is high level; and the grid of the pull-down thin film transistor is connected with the pull-down thin film transistor driving unit, a drain electrode is respectively connected with the signal output terminal, a first capacitor and the drain electrode of the first thin film transistor, and a source electrode is connected with a low voltage signal input terminal. The shift register and the grid driving device for the liquid crystal display can effectively inhibit the noise from being output and can ensure that the large threshold voltage deviation cannot be generated for the shift register and all the thin film transistors in the grid driving device, so that the normal operating life of the shift register and the grid driving device is ensured.

Description

technical field [0001] The invention relates to the field of liquid crystal display, in particular to a shift register and a gate driving device of a liquid crystal display. Background technique [0002] In the existing shift register, the typical structure is Thomson's four-transistor two-capacitor structure, figure 1 Shown is the schematic diagram of the shift register structure, figure 2 shown as figure 1 The input and output timing diagram of the shift register shown. How it works: select figure 2 Part of the timing diagram shown and divided into five stages, in the first stage, the signal input terminal (INPUT) input signal is high level, the reset signal input terminal (RESETIN) input signal is low level, transistor T103 It is turned on, and the transistor T104 is cut off, so the charging of the node PU through the transistor T103 is also high level; in the second stage, the input signal of the signal input terminal (INPUT) is low level, and the input signal of t...

AI Technical Summary

Problems solved by technology

If there are a total of 1000 rows of liquid crystal pixels, and one shift register controls one row of thin film transistors, each shift register is only in the working state for 3T/1000 of the time T during which the liquid crystal display displays a frame of images, and most

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