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Method for manufacturing metal grid structure

A metal gate and gate technology, applied in the field of making metal gate structures, can solve problems such as reducing the effective gate capacitance

Active Publication Date: 2009-10-28
UNITED MICROELECTRONICS CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

If the depletion effect of the polysilicon gate occurs on the polysilicon gate, its effective gate capacitance (EffectGate Capacitance) will decrease

Method used

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  • Method for manufacturing metal grid structure
  • Method for manufacturing metal grid structure
  • Method for manufacturing metal grid structure

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Experimental program
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Embodiment Construction

[0027] Please refer to Figure 1 to Figure 9 , Figure 1 to Figure 9 It is a schematic cross-sectional view of the fabrication process of the metal gate structure according to the first preferred embodiment of the present invention. Such as figure 1 As shown, first a semiconductor substrate 2 is provided, such as a silicon substrate or a silicon-on-insulator (SOI) substrate, etc., and at least one such as shallow trench isolation (shallow trench isolation; STI) is formed in the semiconductor substrate 2. ) or a field oxide (fieldoxide; FOX) etc. isolation region (isolation region) 12 , and due to the standard process of these isolation regions, the isolation region 12 is slightly higher than the surface of the semiconductor substrate 2 . For example, the standard process for forming these isolation regions is an STI process: sequentially forming a pad oxide layer and a hard mask layer on the semiconductor substrate 2; forming shallow trenches; filling the shallow trenches wi...

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Abstract

The invention relates to a method for manufacturing a metal grid structure. The method comprises the following steps: a semiconductor substrate on which an isolation region and an active region are defined is provided; a polysilicon material is formed on the semiconductor substrate; the polysilicon material is flatted and patterned to form at least one first grid and one second grid on the semiconductor substrate, wherein the first grid is positioned in the active region, and the second grid partially bestrides the isolation region; then an interstitial dielectric layer is formed on the semiconductor substrate to cover the grids; the interstitial dielectric layer is flatted until the grids are exposed; the grids are removed to form corresponding grooves in the interstitial dielectric layer; a grid dielectric material is formed on the surfaces of the grooves; and at least one metal material is filled in the grooves.

Description

technical field [0001] The present invention relates to a method for fabricating a gate structure, in particular to a method for fabricating a metal gate structure. Background technique [0002] As the size of CMOS devices continues to shrink, the traditional method of reducing the thickness of the gate dielectric layer, such as reducing the thickness of the silicon dioxide layer, to achieve the purpose of optimization, is facing a problem due to the tunneling effect of electrons. A physical limitation that causes excessive leakage current. In order to effectively extend the generation evolution of logic elements, high dielectric constant (hereinafter referred to as High-K) materials can effectively reduce the physical limit thickness, and at the same equivalent oxide thickness (hereinafter referred to as EOT) Under the advantages of effectively reducing leakage current and achieving equivalent capacitance to control channel switching, it is used to replace the traditional ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/82H01L21/8238H01L21/84
Inventor 林建廷许哲华程立伟
Owner UNITED MICROELECTRONICS CORP