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Insulated source-drain electrode MOD transistor and preparation method thereof

A technology for MOS transistors and manufacturing methods, which is applied in the field of insulated source-drain MOS transistors and their manufacturing, can solve the problems of occupying circuit space, making circuits, free charges cannot flow, etc., achieve high collapse voltage and breakdown voltage, and avoid leakage Phenomenon, the effect of avoiding the floating body effect

Active Publication Date: 2012-11-14
SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

But the insulating layer underneath it keeps these free charges from flowing, which makes the transistor "float" to a certain extent
[0008] Due to the existence of this "floating body effect" (Floating Body Effect, FBE), it is impossible to make existing various circuits on this partially depleted SOI.
In order to eliminate the FBE effect, the designer must introduce an additional ground electrode, which takes up expensive circuit space

Method used

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  • Insulated source-drain electrode MOD transistor and preparation method thereof
  • Insulated source-drain electrode MOD transistor and preparation method thereof
  • Insulated source-drain electrode MOD transistor and preparation method thereof

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Embodiment Construction

[0043] In order to better understand the technical content of the present invention, specific embodiments are given together with the attached drawings for description as follows.

[0044] The invention provides an insulated source-drain MOS transistor and a manufacturing method thereof, which have higher source-drain collapse voltage and breakdown voltage, and can effectively suppress short channel effect and floating body effect.

[0045] Please refer to figure 1 , figure 1 Shown is a structure diagram of an insulated source-drain MOS transistor in a preferred embodiment of the present invention. The insulated source-drain MOS transistor proposed by the present invention includes: a semiconductor substrate 10; a shallow trench 11 located on the semiconductor substrate 10; a source polysilicon 20 and a drain polysilicon 30 respectively located in the shallow trench 11 Inside, there is a channel region 13 between them; the gate insulating layer 40 is located on the channel r...

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Abstract

The invention provides an insulated source-drain electrode MOD transistor and a preparation method thereof. The obtained insulated source-drain electrode MOD transistor comprises a semiconductor underlay, a shallow groove arranged on the semiconductor underlay, source electrode polysilicon and drain electrode polysilicon which are respectively arranged in the shallow groove and a channel area is arranged in between; moreover, the insulated source-drain electrode MOD transistor also comprises a grid insulating layer arranged in the channel area and a grid area arranged on the grid insulating layer; wherein the side wall and the bottom part of the shallow groove are all provided with a pad oxide; the top part of the pad oxide on the side wall is provided with a contact window; the source electrode polysilicon and the drain electrode polysilicon are provided with an epitaxial single crystal silicon layer or a polysilicon layer through chemical vapor deposition at the contact window. The invention provides an insulated source-drain electrode MOD transistor and the preparation method thereof, which has higher source-drain electrode collapse voltage and breakdown voltage, and can effectively inhibit short channel effect and floating body effect.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, and in particular to an insulated source-drain MOS transistor and a manufacturing method thereof. Background technique [0002] Currently, the width of transistors continues to be narrowed due to the trend of miniaturization according to high integration of semiconductor devices. So a hot carrier effect occurs inside the transistor. When the channel length becomes shorter relative to the externally applied voltage, the horizontal electric field is highly concentrated in the drain region to degrade the electrical characteristics of the drain region and generate holes, and here, the hot carrier effect shows The holes move towards the substrate. On the other hand, electrons are trapped under the gate insulating film or spacer, thereby affecting the threshold voltage. The hot carrier effect becomes more severe when a high electric field is applied to the channel of the semiconductor subs...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L29/78H01L29/417H01L29/06H01L21/336
Inventor 孔蔚然
Owner SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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