Adaptable pci express controller core and method

Abstract

A controller core for controlling communication of Peripheral Component Interconnect (PCI) Express, the controller core comprises: a standard configuration register unit, a capabilities register unit, a logic unit and a bond option signal. The standard configuration register unit is configured for controlling the communication of the PCI-E, and supporting the controller core been embedded internally and accessible from exterior. The logic unit applied to associate with the standard configuration register unit and the capabilities register unit for identifying a hot insertion and removal from exterior of the controller core; and the bond option signal is used to enable and disenable the standard configuration register unit, the capabilities register unit, and the logic unit respectively. The invention can be suitable for different sites with reduced manufacture cost and improved manufacture efficiency.

Description

Adaptable PCI-E controller core and its method technical field The invention relates to a peripheral component interconnect (PCI-E, Peripheral Component Interconnect Express) bus device, in particular to a PCI-E bus controller. Background technique In a computer system, a fast and flexible internal communication structure can effectively provide high data transmission capabilities between devices. For example, in the field of data transmission between devices in a computer system, a PCI-E bus can be used to provide a connection between a master device and one or more user devices or terminals. The PCI-E bus was originally called the third-generation input / output bus (3GIO, Third-GenerationI / O), which is a system built on the basis of the peripheral component interconnection (PCI, Peripheral Component Interconnect) bus for servers and client systems. The connected bus is different from the PCI bus based on 32-bit and 64-bit parallel bus. The PCI-E bus adopts high-speed po...

AI Technical Summary

Problems solved by technology

In addition, designing two PCI-E bus chips separately to meet the internal and external application scenarios of the computer system will result in high manufacturing costs

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