Electrostatic discharge testing circuit and correlated method thereof

Abstract

The invention relates to an electrostatic discharge testing circuit and a correlated method thereof. The electrostatic discharge testing circuit comprises a first power source bonding pad, a second power source bonding pad, an RC circuit, a trigger circuit and a bias circuit, wherein the RC circuit comprises a resistor element and a capacitor element; the first power source bonding pad receives afirst supply voltage; the second power source bonding pad is used for receiving a second supply voltage different from the first supply voltage; the resistor element is coupled between the first power source bonding pad and a first terminal, and the capacitor element is coupled between the first terminal and a second terminal; the trigger circuit is used for generating an electrostatic discharge triggering signal according to a voltage level between the first terminal and the second terminal; and the bias circuit is used for supplying a bias voltage to the second terminal.

Description

technical field [0001] The present invention relates to electrostatic discharge protection (ESD protection), in particular to an electrostatic discharge detection (ESD detection) circuit and a related method applied to an electrostatic discharge protection circuit using advanced process components. Background technique [0002] With the advancement of science and technology, the process technology of integrated circuits has also been continuously improved. As known to those skilled in the art, various electronic circuits can be integrated / formed on a chip, and in order to enable the chip to receive an external voltage source (such as a bias power supply) and exchange data with other external circuits / chips, Conductive pads are provided on the chip. For example, in order to transmit the bias voltage, a power pad may be provided on the chip. In addition, signal pads (signal pads), ie input / output pads (I / O pads), are also provided on the chip for receiving input signals and / ...

AI Technical Summary

Problems solved by technology

In other words, when the ESD event does not occur, the tunneling current of the metal oxide semiconductor transistor capacitor 212 will pull down the voltage value of the connection terminal 230 (which connects the capacitive resistance circuit 210 and the inverter circuit 220 ), thus causing The inverter circuit 220 cannot be effectively turned off under normal operation of the chip, resulting in a large amount of leakage current generated between the two power supply pads (between the VDD terminal and the VSS terminal)

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