12 results about "Electrostatic Discharge Testing" patented technology

The utility model relates to the technical field of test tools, in particular to an electrostatic discharge tester fixing tool, which is characterized in that a portal frame is fixed on a base, a vertical lifting sliding table is arranged below the portal frame in a sliding manner, a horizontal product carrying plate is connected to the vertical lifting sliding table, and the product carrying plate is used for placing a product to be tested; a first clamping plate is fixed to the portal frame, a first support plate is vertically fixed to the first clamping plate, a second support plate is vertically fixed to the first support plate, a second clamping plate is connected to the inner side of the second support plate through an adjusting screw, and the position of the second clamping plate corresponds to the position of the first clamping plate. An ESD experimental instrument is clamped and fixed between the second clamping plate and the first clamping plate; the portal frame is connected with an LED lighting assembly used for lighting a product. Compared with the prior art, the fixing jig for the ESD tester has the advantages that by arranging a clamping structure for an ESD experimental instrument, the handheld operation fatigue can be effectively relieved, the product carrier plate can horizontally move and lift, the accurate alignment of an instrument gun head and a product can be favorably realized through the LED illumination and the magnifying glass, and the working efficiency is improved.

The invention discloses a multi-type chip pin positioning method based on binocular vision and a related device, which are applied to alignment of a probe and a chip pin in an electrostatic discharge test, and the method comprises the following steps: obtaining a binocular vision image of a chip to be tested in a CDM discharge test; inputting the binocular vision image of the to-be-tested chip into a pre-trained chip identification model to obtain a chip identification result; performing image processing on the chip contour according to the chip packaging type to obtain a chip pin contour and a pin center point; obtaining the three-dimensional coordinates of the center points of the corresponding pins based on the distance between the center points of the same pin in the binocular vision image; wherein the chip identification model is obtained by improving a YOLOv8n model, and the improvement method comprises the following steps: replacing a Bottleneck structure of a C2f module in the YOLOv8n model by using Faster Block, so that accurate and unmanned chip pin positioning is realized.

The utility model discloses a diaphragm electrostatic discharge testing device, which comprises a base, the top of the base is provided with a supporting bottom plate and a coupling plate, the middle parts of the two ends of the supporting bottom plate in the X-axis direction are respectively connected with a sliding base in a sliding manner, and the two sliding bases are respectively provided with a discharge terminal. The two groups of sliding bases can adjust the distance between the two groups of discharging terminals; two groups of diaphragm clamping plates are vertically arranged in the Y-axis direction of the supporting bottom plate, the two groups of diaphragm clamping plates are used for clamping a diaphragm sample to be tested and are positioned between the two groups of discharge terminals, one end of each discharge terminal is an electrostatic discharge applying end, and the other end of each discharge terminal is connected with the coupling plate. The discharge position of the diaphragm can be adjusted, the purpose of accurately positioning the diaphragm is finally achieved, the discharge state of the diaphragm in the actual machining and using process is simulated, the electrostatic discharge performance of the diaphragm can be screened in the early stage, the quality of the diaphragm is improved, and then the quality of a battery cell is improved.

An electrostatic discharge (ESD) test system disclosed herein comprises: a robot arm including a plurality of joints bent in various directions; an electrostatic discharge (ESD) gun coupled to one end of the robot arm and including a first coupling portion; and a discharge tip including a second coupling portion coupled to the first coupling portion, wherein the first coupling portion includes a first magnet, the second coupling portion includes a second magnet, the first magnet and the second magnet are coupled at a first angle, and a fastening force weakens or a repulsive force is provided at a second angle. The electrostatic discharge (ESD) test system can perform electrostatic discharge tests on electronic devices ranging from small to large devices, thus enabling consistent and accurate testing.

The utility model relates to the technical field of electromagnetic compatibility testing, in particular to an electrostatic discharge testing circuit, a circuit board and testing equipment. The electrostatic discharge test circuit comprises a first switch module, an energy storage module, a second switch module and a test port, wherein the test port is in contact with a tested signal line of a circuit board to be tested. The first switch module is connected with a power supply. And the first switch module is switched on when receiving the charging signal, so that the power supply can charge the energy storage module through the first switch module. And the second switch module is switched on when receiving the trigger signal, so that the energy storage module outputs a test signal to the tested signal line through the test port. According to the circuit, a single excitation function is realized through trigger signal control of the second switch module, an electrostatic discharge test can be excited in a single time by providing a single trigger signal, and the problem that interference pulses are continuously output in a traditional test instrument is avoided; based on the single excitation function, the response condition of the circuit board to be tested under the electrostatic discharge impact can be analyzed more accurately.

In a method of manufacturing an integrated circuit involving performing an electrostatic discharge (ESD) test, a weak frequency band is detected by sequentially radiating a plurality of first electromagnetic waves on a first test board including the integrated circuit. A first peak-to-peak voltage signal is detected by sequentially radiating the plurality of first electromagnetic waves on a second test board including an electromagnetic wave receiving module. A frequency spectrum is detected by radiating a second electromagnetic wave on a housing including a third test board having the electromagnetic wave receiving module. A second peak-to-peak voltage signal is generated based on the weak frequency band, the first peak-to-peak voltage signal, and the frequency spectrum. An ESD characteristic associated with an electronic system including the integrated circuit is predicted based on the second peak-to-peak voltage signal.

Solid state ESD SIC simulator. An electrostatic discharge (ESD) test system includes a FET-based pulse generator that uses a pair of back-to-back FETs coupled to generate an ESD pulse based on discharging a capacitor coupled in series with a device under test (DUT). A number of FETs can be selected based on an expected ESD test voltage amplitude.

The utility model relates to the technical field of power equipment, in particular to an electrostatic discharge simulator with a protection function. The electrostatic discharge simulator with the protection function provided by the utility model comprises two mounting plates, and the number of the mounting plates is two. The electrostatic discharge simulator is mounted between the upper side surfaces of the two mounting plates; the supporting frame is located on the right side of the electrostatic discharge simulator; the automatic electrostatic discharge gun is placed on the support frame; the mute shell is connected to the lower side face of the supporting frame, and the electrostatic discharge simulator and the automatic electrostatic discharge gun are located in the mute shell. According to the utility model, the electrostatic discharge simulator is limited through the limiting plate, the electrostatic discharge simulator and the automatic electrostatic discharge gun cooperate to carry out an electrostatic discharge test on a tested device, and the metal shielding cavity and the mute housing can protect the electrostatic discharge simulator and the automatic electrostatic discharge gun and absorb and reduce noise.

This application provides an electrostatic discharge (ESD) testing system for an Ethernet interface, relating to the field of ESD testing. The system includes: an excitation source device, an Ethernet interface simulation device, and a testing device; the Ethernet interface simulation device is connected to both the excitation source device and the testing device; the Ethernet interface simulation device is a printed circuit board simulating the Ethernet interface of a domain controller; the excitation source device generates a first current conforming to an ESD waveform and injects this first current into the Ethernet interface simulation device; the testing device acquires the output voltage of the Ethernet interface simulation device. Compared to related technologies that rely on prototype testing of domain controllers, the method of this application reduces the complexity of ESD testing for the Ethernet interface of a domain controller.

The invention provides a light-emitting diode screening method, which comprises the following steps of: providing a wafer which is provided with a plurality of light-emitting diode structures; testing each light emitting diode structure on the wafer through wafer-level electrostatic discharge; testing each light emitting diode structure on the wafer by wafer-level collapse voltage; testing the light emitting diode structures on the wafer according to wafer-level photoelectric characteristics; splitting the light emitting diode structures on the wafer to form a plurality of light emitting diode crystal grains; and excluding a part of the light emitting diode crystal grains with abnormity, wherein the abnormity comprises one of electrostatic discharge test abnormity, collapse voltage test abnormity, photoelectric characteristic test abnormity and appearance abnormity.

The application discloses a multi-type chip pin positioning method based on binocular vision and a related device, which is applied to the alignment of probes and chip pins in electrostatic discharge testing, and the method comprises the following steps: acquiring a binocular vision image of a chip to be tested in CDM discharge testing; inputting the binocular vision image of the chip to be tested into a pre-trained chip recognition model to obtain a chip recognition result; performing image processing on a chip contour according to a chip packaging type to obtain a chip pin contour and acquire a pin center point; obtaining three-dimensional coordinates of corresponding pin center points based on the distance between the same pin center points in the binocular vision image; wherein the chip recognition model is obtained by improving a YOLOv8n model, and the improvement method comprises the following steps: replacing a Bottleneck structure of a C2f module in the YOLOv8n model with a FasterBlock, so that accurate and unmanned chip pin positioning is realized.

The embodiment of the utility model relates to the field of electrostatic discharge test, and discloses a test circuit board, which comprises a connection interface and a test module, the connection interface is in communication connection with the test module; the connection interface is configured to be connected with a test device and transmit an electrostatic discharge pulse sent by the test device to the test module so as to perform an electrostatic discharge test on the test module. According to the scheme, the plurality of connection interfaces and the test module are integrated into one test circuit board, so that the test circuit board can represent the electrostatic discharge test of the electronic product main body circuit board. Compared with the situation that signal interference or main body circuit board scrapping is easily caused by direct ESD test on the interface of the main body circuit board of the electronic product, the scheme is used for testing the test circuit board, interference of electrostatic discharge pulses on other signal circuits can be effectively avoided, the cost for testing the scrapped test circuit board through electrostatic discharge is reduced, and the test efficiency is improved. And the test is safer.