Packaging method of chip reconfiguration structure

Abstract

The invention relates to a packaging structure of chip reconfiguration, which comprises a chip, a packaging body, a patterned protection layer, a fan-out patterned metal segment, a second patterned protection layer, a patterned UBM layer and a conductive assembly, wherein the packaging body is annularly covered on four surfaces of the chip so as to expose an active surface and a back surface of the chip out; the patterned protection layer is formed on the surface of the packaging body and covered on the active surface of the chip and exposes a plurality of soldering pads of the chip out; one end of the fan-out patterned metal segment is electrically connected with soldering pads of the chip, and the other end of the fan-out patterned metal segment extends towards the outer side and is covered on the first patterned protection layer; the second patterned protection layer is covered on the patterned metal segment and exposes the partial surface of the patterned metal segment out; the patterned UBM layer is formed on the partial surface of the exposed patterned metal segment; and the conductive assembly is formed on the pattern UBM layer and is electrically connected with the patterned metal segment through the patterned UBM layer.

Description

technical field [0001] The present invention relates to a semiconductor packaging structure and method, in particular to a modular packaging structure formed by using a reconfiguration layer (RDL) after reconfiguring a chip or multiple chips to a carrier with a package and its packaging method. Background technique [0002] Semiconductor technology has developed quite rapidly, so the miniaturized semiconductor chip (Dice) must have diversified functional requirements, so that the semiconductor chip must be configured with more input / output pads (I / O pads) in a small area. O pads), so that the density of metal pins (pins) is also rapidly increased. Therefore, the early lead frame packaging technology is no longer suitable for high-density metal pins; therefore, a ball array (Ball Grid Array: BGA) packaging technology has been developed. The ball array package has the advantage of higher density than the lead frame package. In addition, its solder balls are less prone to da...

AI Technical Summary

Problems solved by technology

[0006] In addition, after the wafer is diced, when the chip needs to be reconfigured on another substrate whose size is larger than the original substrate, due to the need to pass the pick&place device (pick&place) Pick up the chip, turn it over, and attach the active surface of the chip to the substrate in a flip-chip manner. However, during the process of turning the chip over by the pick-and-place device, it is easy to generate tilt and cause displacement, such as : The inclination exceeds 5 microns, so the chip cannot be aligned, and then the subsequent ball planting process cannot be aligned, resulting in a decrease in the reliability of the packaging structure

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