Method for etching dielectric storage layer in flash memory
An electrical storage and storage layer technology, applied in the manufacture of circuits, electrical components, semiconductor/solid-state devices, etc., can solve the problems of corrosion, prolong the time of dry etching, affect the continuation of the process, etc., and achieve the effect of reducing damage
Active Publication Date: 2010-01-06
SEMICON MFG INT (SHANGHAI) CORP
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Therefore, in the case of dry etching, to completely remove the hard mask layer 160, especially the hard mask layer 160 at the recessed portion of the second semiconductor layer 150, it is necessary to prolong the time of dry etching, and prolong the The etching time will cause a certain degree of corrosion on the sharp corners of the recessed edge of the second semiconductor layer 150. In severe cases, the second semiconductor layer 150 at the above position can be completely removed, which will affect the continuation of the subsequent process.
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[0032] The specific implementation of the method for etching the dielectric storage layer in the flash memory provided by the present invention will be described in detail below in conjunction with the accompanying drawings.
[0033] attached Image 6 Shown is a process flow chart of a specific embodiment of the method for etching a dielectric storage layer in a flash memory provided by the present invention. The method includes the following steps: Step S20, providing a semiconductor substrate, a gate dielectric layer, a first semiconductor layer located on the semiconductor substrate in sequence, a shallow trench located in the gate dielectric layer, the first semiconductor layer and the semiconductor substrate; A semiconductor layer and a shallow trench, a continuous dielectric storage layer away from the surface of the semiconductor substrate, a second semiconductor layer, and a hard mask layer with an opening structure; step S21, using the hard mask layer as a barrier lay...
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The invention discloses a method for etching a dielectric storage layer in a flash memory, which provides a semiconductor substrate, a gate dielectric layer, a first semiconductor layer, shallow grooves, a continuous dielectric storage layer, a second semiconductor layer and a hard mask layer, wherein the gate dielectric layer and the first semiconductor layer are positioned on the semiconductor substrate in turn; the shallow grooves are positioned in the gate dielectric layer, the first semiconductor layer and the semiconductor substrate; the continuous dielectric storage layer and the second semiconductor layer are arranged on the first semiconductor layer and the shallow grooves away from the surface of the semiconductor substrate; and the hard mask layer has an opening structure. The method comprises the following steps: by using the hard mask layer as a barrier layer, etching the second semiconductor layer till exposing the dielectric storage layer; removing the hard mask layer; and removing the dielectric storage layer. The method has the advantages that the method separates the processes for removing the hard mask layer and the dielectric storage layer, firstly corrodes the hard mask layer to reduce the damage of the second semiconductor layer under the hard mask layer caused by a corrosion process, and then removes the dielectric storage layer.
Description
【Technical field】 [0001] The invention relates to the field of integrated circuit manufacturing, in particular to a method for etching a dielectric storage layer in a flash memory. 【Background technique】 [0002] In the field of integrated circuit manufacturing, with the continuous reduction of the feature size of integrated circuits and the continuous improvement of chip integration, the traditional production mode, process materials and device models are facing many challenges. [0003] Flash memory is a common memory, which mainly stores charges through a dielectric storage layer to realize data storage and exchange. A typical flash memory chip usually includes a storage unit and a control unit. The storage unit is used to read, write and store charges, so the gate structure in the storage unit has a double-layer dielectric structure and a double-layer conductive structure. The control unit controls the working state of the storage unit through a control circuit formed ...
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Login to View More IPC IPC(8): H01L21/8247H01L21/311
Inventor李雪许宗能杨海玩吴佳特
OwnerSEMICON MFG INT (SHANGHAI) CORP