Temperature self-adaptive adjustment method for read data sampling and device thereof

Abstract

The invention provides a temperature self-adaptive adjustment method for read data sampling and a read data sampling device thereof. The device comprises a clock output circuit, a primary sampling circuit, a data synchronous circuit and a temperature difference compensating circuit, wherein, the temperature difference compensating circuit is used for respectively carrying out secondary sampling on the read data output by the primary sampling circuit with the utilization of sampling clocks CLK21 and CLK22. The method comprises the following steps: delaying and then outputting the read data sampled by the CLK21 to K*T when a working temperature is less than a threshold temperature, otherwise, directly outputting or delaying the read data sampled by the CLK22 to (k-1)*T and then outputting the data; and taking an internal clock of a storage controller or the delayed signal thereof as a sampling clock CLK3 by the data synchronous circuit, and sampling the read data output by the temperature difference compensating circuit or the delayed data thereof. The method can help stably sample the read data under a high temperature and a low temperature without software control.

Description

technical field [0001] The invention relates to data sampling, in particular to a DDR (Double Data Rate, double speed memory) reading data sampling device and sampling method. Background technique [0002] As a large-capacity, high-density fast memory, DDR has been widely used in various chips. The main difference between DDR and the previous generation SDRAM (Synchronous Dynamic Random Access Memory, Synchronous Dynamic Random Access Memory) is that DDR will perform data transmission on the rising and falling edges of the clock, and SDRAM can only transmit data on the rising edge of the clock. And the clock frequency of DDR supports from 133MHz-200MHz, and the clock frequency of SDRAM is generally lower than 133MHz. [0003] The high-speed clock and faster data transfer rate make the DDR read data sampling device the biggest difficulty in design, and the allowable setup and hold time of the data is within 2ns. Affected by temperature, when the data of the DDR chip is at t...

AI Technical Summary

Problems solved by technology

At a speed of 166MHz, a clock cycle is 6ns, so the delay of DQS' relative to DCLK at high temperature is one clock cycle longer than that at low temperature, and it needs to wait one more clock cycle to sample and obtain valid read data DQ_S2, which needs to be used The software performs additional control, which increases the burden on the CPU, and also needs to detect the temperature, and the reliability of reading data will decrease

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