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Phase-locked loop

A phase-locked loop and resistor technology, applied in the field of phase-locked loops, can solve problems such as poor PLL performance, and achieve the effects of reducing locking time, reducing phase error, and improving jitter performance

Inactive Publication Date: 2010-03-17
GRACE SEMICON MFG CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0006] In the low-pass filter in the prior art, the performance of the PLL is poor due to the large variation range of the damping coefficient ζ

Method used

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Embodiment Construction

[0020] The present invention will be described in further detail below in conjunction with the accompanying drawings.

[0021] The phase-locked loop provided by the present invention includes a reference clock, a frequency and phase detector, a charge pump, a low-pass filter, a voltage-controlled oscillator and a frequency divider, and the low-pass filter includes a logic control module, a variable resistor, a first capacitor and the second capacitor; the series circuit composed of the variable resistor and the first capacitor is connected in parallel with the second capacitor; the logic control module is used to adjust the integer N used when dividing the output signal of the voltage-controlled oscillator according to the frequency divider. Vary the resistance value of the resistor to optimize the damping coefficient.

[0022] image 3 It is a structural schematic diagram of the low-pass filter provided by the present invention. The input signal is grounded through the seco...

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Abstract

The invention relates to a phase-locked loop (PLL) comprising a reference clock, a phase frequency detector, a charge pump, a low-pass filter, a voltage-controlled oscillator (VCO) and a frequency divider, wherein, the low-pass filter comprises a logic control module, a variable resistor, a first capacitor and a second capacitor; a series circuit formed by the variable resistor and the first capacitor is connected in parallel with the second capacitor; the logic control module is used for adjusting the resistance of the variable resistor according to the integer N used when the output signalsof the VCO are divided by the frequency divider, so as to optimize the damping factor. The invention can improve the PLL closed-loop stability, reduce the locking time, reduce the phase error and improve the jitter performance.

Description

technical field [0001] The invention relates to the field of electronics, in particular to a phase-locked loop. Background technique [0002] Phase-Locked Loops (PLLs) are widely used in electronic and communication systems for clock and data recovery, frequency synthesis, clock synchronization in microprocessors, and many other applications. like figure 1 As shown, the PLL includes a reference clock, a phase frequency detector, a charge pump, a low-pass filter, a voltage-controlled oscillator (Voltage-controlled oscillator, VCO) and a frequency divider, and the output signal is Vout(t). A wideband PLL can correct VCO errors faster, but if the frequency bandwidth is too wide, it will not reduce the system input noise. [0003] Generally, for an integer N, the output frequency Fout=input frequency Fin×N is modulated by a loop divider (ie, loop divider), which is related to a damping factor (damping factor) ζ. N<7:0>: 2~255 indicates that N is a binary number construc...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03L7/093H03L7/18
Inventor 段新东
Owner GRACE SEMICON MFG CORP