Bit line cutting buffer

Abstract

The invention provides a bit line cutting buffer which is connected in series with two sections or more segmentation registers so as to cut a whole bit line into different series of bit lines. The bit line cutting buffer comprises a level detection circuit and a post bit line discharging control circuit, wherein the level detection circuit comprises a NOT gate made up of P1 and N1; the input end of the NOT gate is connected with a preceding bit line; the post bit line discharging control circuit comprises a NMOS transistor of a drain open circuit; the output end of the level detection circuit is connected with the grid of a post bit line discharging control circuit; the drain output end of the post bit line discharging control circuit is arranged for discharging a lower bit line; and the source of the post bit line discharging control circuit is grounded. A folding bit line cutting method greatly decreases the influence caused by generated extra cascading delay when the series are redundant during the process of dividing. The bit line cutting technique is assisted by a corresponding charging mechanism.

Description

technical field [0001] The present invention relates to a register file with high speed and low power consumption, a bit line segmentation method in an SRAM, a specific implementation of a buffer circuit for bit line segmentation, and a corresponding charging mechanism. Background technique [0002] In the register file, the readout logic of different memory cells shares one bit line. The charging and discharging speed of the bit line is relatively slow. In order to improve the overall performance of the register file, it is necessary to speed up the charging and discharging speed of the read bit line. The traditional method uses a sensitive amplifier to detect the change of the bit line level. When the memory capacity is too large, the method of grouping the memory is adopted, and multiple small-capacity memories are used to form a large memory, but this method requires additional logic such as multiplexers to support. [0003] In the design of the multi-port register fil...

AI Technical Summary

Problems solved by technology

This makes the impact of advanced technology on the load capacitance of the read logic bit line in the register file more serious

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