Manufacturing process for a chip package structure
A chip packaging structure and chip technology, applied in the fields of semiconductor/solid-state device manufacturing, electrical components, electrical solid-state devices, etc., can solve the problems that are not conducive to reducing the total thickness of the chip packaging structure, and cannot effectively reduce the thickness of the core dielectric layer.
Active Publication Date: 2011-10-05
CHIPMOS TECH INC
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Problems solved by technology
Therefore, if the thickness of the core dielectric layer cannot be effectively reduced, it is bound to be unfavorable for reducing the total thickness of the chip packaging structure.
Method used
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[0039] The embodiments of the present invention can refer to the corresponding drawings, and parts with the same number in the drawings or descriptions are the same or similar to each other.
[0040] Figure 1A to Figure 1G It is a cross-sectional view of the manufacturing process of the chip packaging structure according to an embodiment of the present invention. Please refer to Figure 1A , providing a conductive layer 110 and a patterned solder resist layer 120 , wherein the conductive layer 110 has a first surface 112 and a second surface 114 opposite to each other, and the patterned solder resist layer 120 has a plurality of openings 122 . In addition, the patterned solder resist layer 120 is disposed on the first surface 112 of the conductive layer 110 , and the opening 122 exposes part of the first surface 112 of the conductive layer 110 . In a preferred embodiment, a brown oxidation process or a black oxidation process may be applied to the conductive layer 110 to inc...
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A manufacturing process for a chip package structure is provided. First, a patterned conductive layer and a patterned solder resist layer are provided, wherein the patterned solder resist layer is positioned on the patterned conductive layer. A plurality of chips are bonded onto the patterned conductive layer such that the chips and the patterned solder resist layer are respectively disposed at two opposite surfaces of the patterned conductive layer. The chips are electrically connected to the patterned conductive layer by a plurality of bonding wires, wherein the chips and the bonding wires are at the same side of the patterned conductive layer. A package colloid is formed to encapsulate the patterned conductive layer, the chips and the bonding wires. Then, the package colloid, the patterned conductive layer and the patterned solder resist layer are separated. According to the invention, a chip package structure can be manufactured without using a core dielectric layer, and thus, thethickness of the manufacture chip package structure is smaller than that of a chip package structure of the prior art.
Description
technical field [0001] The present invention relates to a manufacturing process of a chip packaging structure, and in particular to a manufacturing process of a thinner chip packaging structure. Background technique [0002] In the semiconductor industry, the manufacturing process of integrated circuits (IC) is mainly divided into three stages: integrated circuit design, integrated circuit manufacturing and integrated circuit packaging. [0003] In the manufacturing process of an integrated circuit, a chip is completed through steps such as wafer fabrication, circuit design, and wafer dicing. The wafer has an active surface, which is the surface on which a plurality of active devices are formed. After forming the integrated circuits in the wafer, a plurality of pads are formed on the active surface of the wafer, so that chips formed by dicing the wafer can be electrically connected to the carrier through the pads. The carrier can be a lead frame or a circuit board. The ch...
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IPC IPC(8): H01L21/50H01L21/782
CPCH01L2224/32225H01L2224/48091H01L2924/15311H01L2224/48227H01L2224/73265H01L2924/014H01L2224/45144H01L24/97H01L2224/97H01L2924/14
Inventor 沈更新林峻莹
Owner CHIPMOS TECH INC