Esd protection circuit and circuitry of ic applying the ESD protection circuit

Abstract

A circuitry of an IC is provided, including a pad, an internal circuit, and an ESD protection circuit. The pad transmits or receives a signal and is coupled to a first node. The internal circuit is coupled to the first node for processing the signal. The ESD protection circuit includes an ESD clamping circuit, a first current limiting and shunting unit and a second current limiting and shunting unit. The ESD clamping circuit is coupled to the first node, for clamping an ESD current flowing through the first node. The first current limiting and shunting unit is through the first node coupled to the pad, for limiting the ESD current and shunting part of the ESD current to a first voltage path. The second current limiting and shunting unit is coupled to the first current limiting and shunting unit, for limiting the ESD current and shunting part of the ESD current to a second voltage path.

Description

technical field

[0001] The present invention relates to an electrostatic discharge (ESD) protection circuit and an integrated circuit, and more particularly, to an ESD protection circuit and an integrated circuit using a diffusion resistor and a parasitic diode. . Background technique

[0002] From the perspective of the development of semiconductor manufacturing process, the size of complementary metal-oxide-semiconductor (hereinafter referred to as CMOS) transistors has reached the sub-micron level, which improves the very large scale integration. , hereinafter referred to as VLSI) circuit performance and calculation speed. As the size of the VLSI circuit is reduced, the ESD tolerance and reliability of the VLSI circuit are also greatly reduced.

[0003] The ESD model includes a human-body model (HBM), a machine model (MM) and a charged-device model (CDM). All three models generate transient currents of several amperes that last only for hundreds or even nanoseconds. ...

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