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Modulation method and implementation circuit for unit vector to carrying out time-delay superimposition of multi-level space vector

A modulation method and space vector technology, which are applied to electrical components, output power conversion devices, and AC power input to DC power output, etc., can solve problems such as complex calculation methods, achieve convenient and flexible control, improve control performance, reduce The effect of system resource requirements

Inactive Publication Date: 2010-06-16
HARBIN INST OF TECH
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Problems solved by technology

[0003] The purpose of the present invention is to provide a modulation method and an implementation circuit for superimposing multi-level space vectors with a unit vector time delay, which solves the problem that cascaded inverters are modulated by traditional multi-level SVM methods and require vector selection and calculation methods complicated question

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  • Modulation method and implementation circuit for unit vector to carrying out time-delay superimposition of multi-level space vector
  • Modulation method and implementation circuit for unit vector to carrying out time-delay superimposition of multi-level space vector
  • Modulation method and implementation circuit for unit vector to carrying out time-delay superimposition of multi-level space vector

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specific Embodiment approach 1

[0014] Specific implementation mode one: the following combination Figure 1-Figure 4 Describe this embodiment, this embodiment comprises the following steps:

[0015] Step 1: The left bridge arm and the right bridge arm of the three H-bridge inverters of each level unit of the three-phase N-level unit cascaded inverter are equivalent to the left bridge arm equivalent inverter and the right bridge arm respectively Arm equivalent inverter, so that the output voltage vector of each level unit of the three-phase N-level unit cascaded inverter is equivalent to the output voltage vector of the left bridge arm equivalent inverter and the right bridge arm equivalent inverter The difference, N is a natural number greater than 1;

[0016] Step 2: Set the calculation period of the three-phase N-level unit cascaded inverter as T s , the number of units is i, i is a natural number and i≤N, at the beginning of each calculation cycle, the left side of the first-level unit of the three-pha...

specific Embodiment approach 2

[0028] Specific implementation mode two: the following combination Figure 5-Figure 8 Describe this embodiment, this embodiment is made up of DSP chip 1 and FPGA field programmable gate array 2, and FPGA field programmable gate array 2 is made up of data latch module 2-1, decoding module 2-2, voltage vector module 2- 3. Dead time module 2-4, PWM control module 2-5, counter period value module 2-6, counter group 2-7, N PWM generators 2-8 and N signal interlock modules 2-9 ,

[0029] The control data output end of DSP chip 1 is connected to the control data input end of data latch module 2-1, the address signal output end of DSP chip 1 is connected to the address signal input end of decoding module 2-2, and the address signal input end of decoding module 2-2 The module selection enable signal output terminal is connected to the address signal input terminal of the data latch module 2-1, wherein the address signal received by the data latch module 2-1 corresponds to the control ...

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Abstract

The invention relates to modulation method and implementation circuit for a unit vector to carrying out the time-delay superimposition of a multi-level space vectors, belonging to the field of electrical energy conversion and solving the problem that a cascading type inverter is modified by adopting a traditional multi-level SVM (Support Vector Machine) method, vector selection is needed, and a calculating method is complicated. The modification method comprises the following steps of: equalizing the unit of each stage of a three-phase N-stage unit cascading type inverter into two double-level three-phase inverters; calculating the output voltage vector of a left bridge arm equivalent inverter of the first-stage unit at the beginning time of a calculating period by adopting a double-level space vector modification method; acting the voltage vector on a left bridge arm equivalent inverter of an ith-stage unit after the voltage vector is delayed by (i-1)Ts / 2N; and after delaying, acting on a right bridge arm equivalent inverter of the ith-stage unit so as to realize the output of a multi-level PWM voltage wave form. The implementation circuit consists of a DSP (Digital Signal Processor) chip and a field programmable gate array (FPGA). The invention is used for Modulating the multi-level space vector of the cascading type inverter.

Description

technical field [0001] The invention relates to a modulation method and a realization circuit for unit vector time-delay superposition of multi-level space vectors, and belongs to the field of electric energy conversion. Background technique [0002] The cascaded multi-level inverter realizes the electric energy conversion in the high-voltage field by cascading multiple low-voltage H-bridge units. and other fields have been widely used. As an important factor that directly determines the control effect of the inverter - the multi-level PWM method has received widespread attention from scholars at home and abroad, and a lot of research work has been carried out. At present, the multi-level PWM methods of the cascaded inverter mainly include the carrier phase-shifted SPWM (CPS-SPWM) method, the multi-level SVM method and the selective harmonic elimination PWM (SHEPWM) method and the like. Among them, the CPS-SPWM method achieves multi-level output waveforms by staggering the...

Claims

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Application Information

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IPC IPC(8): H02M7/5387
Inventor 吴凤江赵克孙力孙立志王有琨孙光亚吴重祥修永文
Owner HARBIN INST OF TECH
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