Modulation method and implementation circuit for unit vector to carrying out time-delay superimposition of multi-level space vector
A modulation method and space vector technology, which are applied to electrical components, output power conversion devices, and AC power input to DC power output, etc., can solve problems such as complex calculation methods, achieve convenient and flexible control, improve control performance, reduce The effect of system resource requirements
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[0014] Specific implementation mode 1: the following combination Figure 1-Figure 4 To describe this embodiment, this embodiment includes the following steps:
[0015] Step 1: Convert the left bridge arm and right bridge arm of the three H-bridge inverters of each level unit of the three-phase N-level unit cascade inverter to the left bridge arm equivalent inverter and the right bridge respectively Arm equivalent inverter, so that the output voltage vector of each level unit of the three-phase N-level unit cascaded inverter is equivalent to the output voltage vector of the left-side equivalent inverter and the right-side equivalent inverter The difference between, N is a natural number greater than 1;
[0016] Step 2: Set the calculation period of the three-phase N-level unit cascaded inverter as T s , The number of stages of the unit is i, i is a natural number and i≤N. At the beginning of each calculation cycle, the two-level space vector modulation method is used to calculate th...
Example Embodiment
[0028] Specific implementation manner 2: the following combination Figure 5-Figure 8 To describe this embodiment, this embodiment consists of a DSP chip 1 and an FPGA field programmable gate array 2. The FPGA field programmable gate array 2 consists of a data latch module 2-1, a decoding module 2-2, and a voltage vector module 2- 3. Dead time module 2-4, PWM control module 2-5, counter period value module 2-6, counter group 2-7, N PWM generators 2-8 and N signal interlock modules 2-9 ,
[0029] The control data output terminal of the DSP chip 1 is connected to the control data input terminal of the data latch module 2-1, the address signal output terminal of the DSP chip 1 is connected to the address signal input terminal of the decoding module 2-2, and the address signal input terminal of the decoding module 2-2 The module selection enable signal output terminal is connected to the address signal input terminal of the data latch module 2-1, where the address signal received by ...
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