Synchronous display device, stacking splicing display system and synchronous display method thereof

Abstract

The invention relates to a synchronous display device and a synchronous display method. The device comprises a synchronous control circuit, more than one mainboards and more than two display cards. Any one of mainboards is inserted with at least one display card. The synchronous control circuit comprises a frame synchronous control circuit and a reference clock generating circuit. A signal output end of the frame synchronous control circuit is connected with a signal input end of each mainboard. A signal output end of the reference clock generating circuit is connected with a clock signal input end of each display card. The frame synchronous control circuit generates a reference frame synchronous signal or uses a frame synchronous signal of a display channel of a preset display card as the reference frame synchronous signal. Each mainboard adjusts the frame synchronous signal of the display channel of the corresponding display card according to the reference frame synchronous signal. The invention adopts the same reference frame synchronous signal and reference clock signal to together complete synchronous display, cannot generate the clock error and also cannot generate the accumulated error among the frame synchronous signals so as to improve accuracy and continuity of synchronization among the display signals.

Description

technical field [0001] The present invention relates to the technical field of image display, in particular to a synchronous display device and a synchronous display method for the synchronous display device, a superimposed display system, and a spliced ​​display system. Background technique [0002] The patent application with application number 200810198074.5 and publication number CN101383913A discloses a display superimposition control system and its control method. The system includes a superposition control circuit, a frame synchronization control circuit, a display and at least two display signal output devices. Each display The display output terminal of the signal output device is electrically connected with the superposition control circuit, the frame synchronization control circuit is electrically connected with the control signal input terminal of each display signal output device, and the superposition control circuit, and the superposition control circuit is ele...

AI Technical Summary

Problems solved by technology

[0007] The above-mentioned ±10ppm is equivalent to ten millionths, and the frame frequency of most displays is 60Hz at present, and the cycle is 1 / 60 second, which is 0.017 seconds. Calculated according to ±10ppm, the cumulative error of one hour is 3600 seconds* 10 / 1000000=0.036 seconds, and the error of 0.036 seconds is far greater than the frame period of 0.017 seconds. In order to make the system last for 8 hours a day, and the cumulative error of multiple frame synchronization signals is less than 10% of the frame period of 0.017 seconds, this is quite difficult

[0008] Therefore, since the basic indicators of the oscillator are related to the output frequency, the influence of frequency accuracy, temperature stability, aging rate, etc. will cause an error between the actual output frequency domain of the oscillator and the ideal frequency, so that each display card There will be accumulated errors in the crystal or crystal oscillator, so it is often necessary to use the method in the application number 200810198074.5 for synchronous correction

However, for all kinds of mature display cards, especially for GPU display cards, it is extremely difficult to modify their parameters, and most manufacturers do not allow customers to modify local parameters, only through the overall The setting of the display parameters is completed, so the response time is not timely, and the display output will be interrupted momentarily, resulting in jittering of the displayed image or an instant black screen or instant blurred screen

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