Control system and method for storage access

Abstract

The invention relates to control system and method for storage access, wherein the control system comprises an access command temporary storage device of a system storage, a storage access and concurrent processing device, an access command temporary storage device of a dynamic storage and a command control device of the dynamic storage, wherein the access command temporary storage device of the system storage is used for temporarily storing an access command of the system storage; the storage access and concurrent processing device is used for decoding the access command of a current system storage so as to generate the access command of the dynamic storage and carrying out priority processing on the access command of the dynamic storage so as to generate the access command of the dynamic storage with the priority; the access command temporary storage device of the dynamic storage is used for temporarily storing the access command of the dynamic storage; and the command control device of the dynamic storage is used for accepting the access command of the dynamic storage and carrying out priority processing on the access command of the dynamic storage so as to generate the access command of the dynamic storage with the priority and generate a control command accessed by the dynamic storage according to the priority.

Description

technical field [0001] The invention relates to the technical field of dynamic memory access, in particular to a control system and method for synchronous dynamic memory access. Background technique [0002] Due to the advancement of semiconductor technology, the operation speed of the dynamic memory has gradually increased. In the past two decades, the operating speed of dynamic memory has increased from several MHz to several GHz, and the number of delay cycles for data access of stable memory has gradually increased. For example, the number of delay cycles for data access of the stable memory bank of SDR is 3-5, while the number of delay cycles for data access of the stable memory bank of DDR-II and DDR-III is 12-25. [0003] A computer system or an image processing system includes multiple system bus masters. Each system bus master device has specific functions, such as: image decoding, image encoding, image playback, audio decoding, audio playback, direct memory acces...

AI Technical Summary

Problems solved by technology

Although this method is comparable figure 1 It saves multiple clock cycles. However, due to the discontinuity of the data address, the system often accesses memory with similar addresses, that is, the system often accesses different pages of the same memory bank of the memory multiple times, so if figure 2 The probability of this interleaved access mode to different memory banks is not high, especially in complex systems, so the known memory access control system still has many shortcomings and needs to be improved

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