Dynamic local reconfigurable system for real-time fault tolerance of hardware

Abstract

The invention relates to a dynamic local reconfigurable system for real-time fault tolerance of hardware. The existing chip redundant resources are not fully utilized, and the hardware resources have low utilization ratio and large power consumption. The dynamic local reconfigurable system comprises a hardware global static area and two hardware dynamic local reconfigurable areas, wherein the hardware global static area comprises a processor system, a clock management module, a decision maker of a real-time error-detecting tracking hardware reconfigurable module, a display control module and a display module; and each hardware dynamic local reconfigurable area is a local reconfigurable module with the same function. The dynamic local reconfigurable system realizes the real-time fault tolerance of the hardware in the reconfigurable area and has the effects of real-timeness, easy upgrading of the product, suitable working under severe environment and prolonged life cycle of the system.

Description

technical field [0001] The invention belongs to the field of electronic technology, relates to a field programmable gate array reconfigurable technology, in particular to a hardware real-time fault-tolerant dynamic partial reconfigurable system. Background technique [0002] In recent years, the basic structure and scale of Field Programmable Gate Array (FPGA) have undergone great changes. Because it combines the flexibility of general-purpose processors and the high performance of ASICs, it has increasingly become the preferred platform for embedded development. At present, based on the principle of FPGA dynamic reconfigurable technology, there are special researches on fault-tolerant processing of reconfigurable systems, which are mainly divided into hardware fault-tolerant and software fault-tolerant. However, hardware fault-tolerant technology based on dynamic partial reconfigurable has a wide range of applications The application prospect is of great significance and pr...

AI Technical Summary

Problems solved by technology

[0003] The resource utilization of FPGA is limited, and it is difficult to improve the general utilization of 70%. As the scale of embedded application design becomes larger and larger, the existing FPGA hardware resources have been difficult to meet the hardware resources required by super-large designs. , how to make full use of redundant hardware resources as fault-tolerant backup resources, and meet the challenges of hardware fault tolerance in large-scale applications

The hardware circuit of the traditional embedded system is fixed, and the implemented functional units cannot be changed on site, so that the system with such an architecture will paralyze the entire system due to problems with local functional units. It is extremely unsuitable for use in aerospace, deep sea and other fields with harsh temperatures, so a self-fault-tolerant hardware system is required to adapt to special environments

Most current reconfigurable fault-tolerant systems are implemented by static global reconfigurable methods, but fault-tolerant systems based on this technology require the system to stop working during the fault-tolerant configuration process, which greatly reduces system performance and flexibility. The entire FPGA needs to be reconfigured to change the operating logic. The reconfigurable part of the system is only configured once, or while some logic units of the FPGA are running, the reconfiguration will affect other running logic modules. Based on this technology The fault-tolerant system cannot guarantee the normal operation of the entire system during fault-tolerant processing, and it is an offline or online fault detection proposed for non-real-time systems, and it cannot guarantee the real-time performance of hardware fault-tolerant processing tasks.

[0004] Due to the limitations of the above aspects, there are such problems: 1. The redundant resources of the FPGA chip are not fully utilized, the utilization rate of hardware resources is low, and the power consumption is large, which fundamentally cannot solve the bottleneck of the repeated use of some FPGA resources.

2. The cost of hardware recovery and maintenance under harsh conditions and the replacement of large-scale hardware equipment are high and the cycle is long, so that it is impossible to realize under certain circumstances

3 There is no guarantee that the entire system will work normally during fault-tolerant processing, nor can it maintain real-time performance

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