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EEPROM circuit for automatically reading and validating data and implementing method thereof

An automatic readout and circuit generation technology, applied in the field of microelectronics, can solve problems such as high power consumption and complex circuit structure, and achieve the effects of reducing power consumption, simplifying the user interface, and reducing complexity

Inactive Publication Date: 2010-09-01
PEKING UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Generally, a special external readout control unit is required to control the reading of data in the EEPROM storage unit, the circuit structure is more complicated, and the power consumption is higher

Method used

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  • EEPROM circuit for automatically reading and validating data and implementing method thereof
  • EEPROM circuit for automatically reading and validating data and implementing method thereof
  • EEPROM circuit for automatically reading and validating data and implementing method thereof

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Embodiment Construction

[0019] The present invention will be further described below in conjunction with a specific embodiment of a MEMS micro-accelerometer readout circuit, but the application of the present invention is not limited to the following specific implementation examples.

[0020] refer to figure 1 , the present invention comprises a self-generated circuit and EEPROM array of readout logic, and the self-generated circuit of readout logic comprises a resistor, a capacitor and a buffer amplifier structure (can be made up of one or more pairs of complementary MOS transistors) (such as figure 2 ); EEPROM array, including a plurality of parallel EEPROM cells, each cell includes a Bitcell of EEPROM (such as image 3 ), that is, a double-gate structure MOS transistor (such as Figure 4 ), the control logic of a Bitcell (with but not limited to the function of making the data read in the Bitcell and closing the Bitcell), and a D latch with high voltage to low voltage conversion and delay, the D...

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PUM

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Abstract

The invention provides an EEPROM circuit design for automatically reading and validating data after a chip is powered on, and belongs to the field of microelectronics. The design is characterized in that when the chip of an EEPROM circuit is powered on, a read-out logic signal is generated through a self-generating circuit of a read-out logic; and the read-out logic signal is input to a Bitcell control logic of each EEPROM unit in an EEPROM array to serve as a control signal so as to read out the data stored in the EEPROM array, meanwhile, the read-out logic signal is used as a clock signal of a latch or a trigger of each EEPROM unit so as to put and store the data read from the EEPROM into a latch or trigger array, close the EEPROM unit and place the EEPROM unit in a low power consumption state. The design self-generates a read-out time sequence to transmit the data to other modules, and can control the EEPROM unit array to enter the low power consumption state so as to reduce the complexity of circuit design on a PCB, simplify a user interface, facilitate the use of the chip and reduce the power consumption.

Description

technical field [0001] The invention belongs to the technical field of data readout structure and readout method in the field of microelectronics, in particular to an EEPROM circuit design in which data is automatically read out after the chip is powered on. Background technique [0002] A large number of circuits in the field of microelectronics need to read out the internal pre-stored data when starting up, as an initial bias or other purposes. EEPROM is the most mainstream non-volatile storage technology used to store such data. EEPROM work has dual voltage characteristics. Reading data only requires standard operating voltage operation, while modifying stored content requires high voltage (generally 12-20V) operation. When the EEPROM is read, it will be turned on and generate current. It is not suitable as a long-term data source. Therefore, the data stored in the EEPROM array is read out and stored in the D latch array. After latching, the EEPROM is turned off or set ...

Claims

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Application Information

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IPC IPC(8): G11C7/06
Inventor 陈中建杨森张明明雷科黄靖清鲁文高张雅聪苏卫国高成臣郝一龙
Owner PEKING UNIV