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Circuit and method for realizing FFT/IFFT conversion

A circuit and complex number addition technology, applied in the direction of electrical digital data processing, reliability improvement and modification, complex mathematical operations, etc., can solve the problem of different data storage order, achieve the effect of reducing operation bit width, saving RAM consumption, and reducing costs

Inactive Publication Date: 2012-06-06
ZTE CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

It also has the disadvantage of the former, namely: the storage order of the data in the RAM before and after the FFT is different, it needs to reorder the data, or like the former, read the data of the butterfly operation every two clocks

Method used

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  • Circuit and method for realizing FFT/IFFT conversion
  • Circuit and method for realizing FFT/IFFT conversion
  • Circuit and method for realizing FFT/IFFT conversion

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Embodiment Construction

[0041] Below in conjunction with accompanying drawing and embodiment the present invention is described in further detail:

[0042] see image 3 , shown in this figure is the circuit realizing FFT / IFFT conversion of the present invention, comprising: multiplexer (A), multiplexer (B), RAM memory 1 (C), RAM memory 0 (D), ROM Memory (E), multiplexer (F), multiplexer (G), complex multiplier (H), complex adder (J), complex adder (K); the output of this circuit is multiplexed The data output of the device (F) and the multiplexer (G), or the data output of the RAM memory 1 (C) and the RAM memory 0 (D); this circuit has two data inputs, respectively connected to the multiplexer (A) and multiplexer (B);

[0043] Wherein, one data input end of FFT / IFFT and the output end of complex number adder (J) are connected with two input ends of multiplexer (A) respectively; Another data input end of FFT / IFFT is connected with complex number adder ( The output end of K) links to each other with...

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Abstract

The invention discloses a circuit and a method for realizing FFT / IFFT conversion. The method comprises the following steps of: 1) determining iterations m, depths d1 of first and second RAMs and depth d2 of an ROM; 2) storing front and back n / 2 parts of input data to be converted in the second and first RAMs respectively; 3) performing m iterative butterfly operations: in the first iteration, reading the first and second RAMs in a bit-reversed order, writing results of even butterfly operations into the first RAM and writing the results of odd butterfly operations into the second RAM; in the second to the (m-1)th iterations, reading the first and second RAMs in a normal bit order and writing back the RAM in the same mode as that in the first iteration; and in the mth iteration, reading the first and second RAMs in the normal bit order, wherein the position for writing back the RAM is the same as the reading position. By using the circuit and the method, the complexity of the circuit can be reduced, the storage order of the data in the RAM is kept the same before and after the conversion, and the extra time consumption is reduced.

Description

technical field [0001] The invention relates to the field of digital signal processing, in particular to a circuit and method for realizing FFT / IFFT transform (fast Fourier transform / fast Fourier inverse transform). Background technique [0002] In digital signal processing, it is often necessary to convert the data from the time domain to the frequency domain. At this time, the FFT transformation is generally used, and the IFFT transformation is used when converting from the frequency domain to the time domain. [0003] FFT can greatly reduce the calculation amount of DFT (Discrete Fourier Transform). For N-point DFT transformation, the calculation amount is N 2 , the calculation amount of base 2 FFT is Nlog 2 N. [0004] There are many forms of FFT transformation, such as time domain decimation / frequency domain decimation, base 2 / base 4 / base 8 / split base and other combinations. FFT transformation generally requires multiple iterations to complete. For example, radix-2 t...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F17/14H04L27/26H03K19/003
CPCG06F17/142H04L27/26
Inventor 温子瑜
Owner ZTE CORP