Clock circuit control device in digital-analog mixed chip and method thereof

Abstract

The invention discloses a clock circuit control device in a digital-analog mixed chip and a method thereof. The device comprises a transmission unit, a time delay unit, a clock source, a power supply, a control switch unit, a power-on reset detection circuit, a reset synchronous circuit and a gated clock, wherein the transmission unit is connected with the control switch unit and simultaneously connected with the clock source through the time delay unit, and a start-stop signal generated by the transmission unit determines whether to conduct the control switch unit and controls whether the clock source generates a digital clock signal; the power supply is connected with the clock source; the power-on reset detection circuit is connected with the power supply through the control switch unit and is used for generating a reset control signal; the reset synchronous circuit is connected with the clock source and the power-on reset detection circuit and is used for generating a synchronous reset signal; and the gated clock is connected with the clock source and the reset synchronous circuit and controls whether the digital clock signal enters a digital circuit according to the synchronous reset signal. By adopting the device and the method provided by the invention, stable operation of each circuit can be ensured during the start-stop period of the chip.

Description

technical field [0001] The invention relates to the field of integrated chip design, more specifically, to a clock circuit control device and method in a digital-analog hybrid chip. Background technique [0002] In the field of wireless communication technology, terminal products are changing with each passing day, with increasingly rich applications and more and more hardware functions, which put forward higher requirements for the battery life of terminal products. Especially for the current third-generation mobile communication standard - Time Division-Synchronous Code Division Multiple Access (TD-SCDMA) terminals, high power consumption and heat generation are one of the factors restricting the development of its terminal products . In the case that the capacity of the battery has not been greatly improved, reducing the overall power consumption of the terminal has become an effective means to improve its battery life. [0003] One of the effective means to reduce the ...

AI Technical Summary

Problems solved by technology

Similarly, when the chip enters the dormant state from the receiving or transmitting working state, the digital clock signal is out of sync with the reset control signal, making the clock input of the digital circuit in an unsteady state, which will also cause the chip to work abnormally

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