NPN transistor and fabricating method thereof

Abstract

The invention provides an NPN transistor and a fabricating method thereof, wherein the NPN transistor comprises a semiconductor substrate, an N-type buried layer region positioned in the semiconductor substrate, a collector electrode positioned in the N-type buried layer region, base electrodes positioned on the N-type buried layer region and the collector electrode, a second oxidization layer positioned on the surface of the base electrodes, an emitting electrode, shallow-doped metal contacts positioned in the base electrodes at two sides of the emitting electrode, side walls positioned at two sides of the emitting electrode and the second oxidization layer and deep-doped regions positioned in the emitting electrode and the base electrodes at two sides of the side walls, wherein the second oxidization layer is internally provided with a contact hole penetrating the thickness of the second oxidization layer; the emitting electrode is filled in the contact hole and cover the surface of the second oxidization layer around the contact hole; and the deep-doped regions are deeper than shallow-doped regions in the base electrodes. The invention can greatly reduce the series resistance, and can lower the influence of side and transient diffusion.

Description

technical field [0001] The invention relates to the field of semiconductor device manufacturing, in particular to an NPN transistor and a manufacturing method thereof. Background technique [0002] Bipolar transistors are one of the device structures that constitute modern large-scale integrated circuits. Bipolar transistors have the advantages of fast operation speed, large output current per unit chip area, and small changes in conduction voltage, which are suitable for making analog circuits. [0003] With the continuous development of semiconductor technology, the performance requirements of devices are getting higher and higher, and the performance requirements of bipolar transistors (such as NPN transistors) are also correspondingly increased. [0004] The existing process for forming NPN transistors is as follows: figure 1 As shown, a semiconductor substrate 100 is provided, and the material of the semiconductor substrate 100 can be silicon or silicon germanium, etc....

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Problems solved by technology

[0008] The NPN transistor formed by the prior art reduces the series resistance due to one-time high-dose and high-energy ion implantation at the emitter 110 and the base 106, but it will cause negative effects of lateral and transient diffusion

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