Interlock of read column select and read databus precharge control signals

Abstract

A column select and databus precharge signal interlock scheme for a DRAM memory. The signal interlock system includes column read enable circuits associated with each bank of a DRAM memory for generating column select signals for coupling data to a common read databus, and a read databus precharge disable signal for disabling read databus precharge devices. Each column read enable circuit includes pulse generator circuits with tunable components for generating at least one column select signal pulse and the read databus precharge disable pulse in a read operation. The pulse generator circuits ensure that the column select pulse is always nested with respect to the read databus precharge disable pulse. Therefore, there is no overlap between active column select devices and active read databus precharge devices.

Description

technical field [0001] The present invention relates generally to semiconductor memories. More specifically, the present invention relates to column selection and precharge signal timing control. Background technique [0002] DRAM memories are widely used in computer systems due to their high density and high performance relative to other available memories. DRAM memory can be used in other applications such as hard disk drive cache to quickly access large amounts of data storage. Although the performance of SRAM is comparable, SRAM memory cells are relatively large, resulting in a low storage density per cell area of ​​the chip. On the other hand, flash memory has better storage density than DRAM, but read and write (program) performance is relatively poor. Thus, DRAM offers the best balance between storage density and performance. [0003] Those of ordinary skill in the art should be very familiar with DRAM architecture. A DRAM memory array includes rows of word lines...

AI Technical Summary

Problems solved by technology

In order to account for the propagation delay of the signal to ensure data integrity, more timing margin can be provided, but this will cause the device to perform slower

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