System and method for extracting parasitic components in analog integrated circuit layout

Abstract

The invention discloses a system and method for extracting parasitic components in an analog integrated circuit layout, which is designed to mainly optimize integrated circuit design and extract the parasitic components in different manufacturing processes. The system comprises a data reading module, a layer defining module, a parasitic component extraction rule module and a parasitic component extraction module, wherein the data reading module is used for reading the data of the analog integrated circuit layout; the layer defining module is used for describing the correspondence between geometric layers and physical layers in the layout; the parasitic component extraction rule module is used for making the extraction rule of the parasitic components and generating extraction rule execution files; and the parasitic component extraction module is used for pretreating the received data output by the data reading module, operating and extracting the received data based on the layer defining module and the parasitic component extraction rule module, marking the extracted parasitic components in the analog integrated circuit layout and outputting the analog integrated circuit layout containing the parasitic components. The invention can extract the parasitic components in different manufacturing processes and provide basis for layout optimization design.

Description

technical field [0001] The invention relates to the field of analog integrated circuit design, in particular to the field of integrated circuit design optimization. Background technique [0002] An analog integrated circuit refers to an integrated circuit that integrates analog circuits composed of resistors, capacitors, and transistors on silicon chips to process analog signals. Integrated circuits are designed by designers with the help of Electronic Design Automation (EDA, Electronic Design Automation) tools to design integrated circuit layouts, delivered to integrated circuit manufacturers, through the preparation of circuit masks (Mask), and the oxidation and doping of wafers (Wafer). A series of manufacturing processes such as miscellaneous and photolithography transfer the circuit mask to the wafer to realize its circuit function. However, in the manufacturing process of integrated circuits, different circuit mask layers will form special structures in certain areas....

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Problems solved by technology

However, for the design of analog integrated circuits under special processes, such as high-voltage and high-power layout design, some special parasitic structures will be generated due to the high voltage of some nodes in the layout, and these structures cannot be extracted by general-purpose EDA tools. At present, this part of the work basically relies on the designer's design experience and spends a lot of time and energy to complete it. There is no special tool to extract the special parasitic devices under the special process.

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