Semiconductor photoelectric structure for improving light extraction efficiency and manufacturing method thereof

[0073] The direction of the present invention discussed here is a semiconductor optoelectronic device structure and its manufacturing method for improving light extraction efficiency. In order to thoroughly understand the present invention, detailed steps and their composition will be proposed in the following description. Obviously, the implementation of the present invention is not limited to the specific details known to those skilled in semiconductor optoelectronic technology. On the other hand, well-known components or steps are not described in details to avoid unnecessary limitation of the present invention. The preferred embodiments of the present invention will be described in detail as follows. However, in addition to these detailed descriptions, the present invention can also be widely implemented in other embodiments, and the scope of the present invention is not limited, and the following claims shall prevail. .

[0074] An object of the present invention is to improve the light extraction efficiency of the light-emitting diode structure, thereby increasing the light-emitting brightness of the light-emitting diode.

[0075] Another object of the present invention is to reduce the defect density of the epitaxy process and improve the quality of the epitaxy.

[0076] In order to achieve the above-mentioned object, the present invention provides a semiconductor optoelectronic element structure with improved light extraction efficiency. The structure includes: a substrate, a buffer layer on the substrate, wherein the buffer layer has a continuous hole pattern between the buffer layer and the substrate, a semiconductor layer is on the buffer layer, and the semiconductor layer includes: An n-type conductive layer is located on the buffer layer, a light-emitting layer is located on the n-type conductive layer, a p-type conductive layer is located on the light-emitting layer, a transparent conductive layer is located on the semiconductor layer, and a p-type electrode It is located on the transparent conductive layer, and an n-type electrode is located on the n-type conductive layer.

[0077] The present invention further provides a semiconductor optoelectronic device structure for improving light extraction efficiency. The structure includes: a substrate, a buffer layer on the substrate, wherein the buffer layer has a continuous hole pattern in the middle, and a semiconductor layer is on the buffer layer Above, wherein the semiconductor layer includes: an n-type conduction layer on the buffer layer, a light-emitting layer on the n-type conduction layer, a p-type conduction layer on the light-emitting layer, and a transparent conductive layer on the On the semiconductor layer, a p-type electrode is on the transparent conductive layer, and an n-type electrode is on the n-type conducting layer.

[0078] In addition, the present invention provides a method for manufacturing a semiconductor optoelectronic device with improved light extraction efficiency. The method includes the following steps: providing a substrate, forming a patterned silicon dioxide layer on the substrate, and forming a filling layer on the patterned substrate. On the silicon dioxide layer, a semiconductor layer is formed on the filling layer. After removing the patterned silicon dioxide layer, a continuous hole is formed between the substrate and the filling layer. The semiconductor layer is etched to form a cutting platform. A transparent conductive layer is formed on the aforementioned semiconductor layer.

[0079] The present invention further provides a method for manufacturing a semiconductor optoelectronic device with improved light extraction efficiency. The method includes the following steps: providing a substrate, forming a buffer layer on the substrate, and forming a patterned silicon dioxide layer on the buffer layer On the above, a filling layer is formed on the patterned silicon dioxide layer, and a semiconductor layer is formed on the filling layer. After removing the patterned silicon dioxide layer, a continuous hole is formed between the substrate and the filling layer. Etching the semiconductor layer to form a cutting platform, and forming a transparent conductive layer on the semiconductor layer.

[0080] The semiconductor layer of the present invention further includes an electron blocking layer located between the light-emitting layer and the p-type conductive layer.

[0081] The present invention further includes an insulating layer covering the p-type conducting layer and the n-type conducting layer and exposing the p-type electrode and the n-type electrode.

[0082] The insulating layer of the present invention can be silicon dioxide (SiO 2 ), epoxy resin (Epoxy), silicon nitride (Si 3 N 4 ), titanium dioxide (TiO 2 ) Or aluminum nitride (AlN).

[0083] The continuous hole surface of the present invention can be a flat surface or a roughened surface.

[0084] The surface of the p-type conductive layer of the present invention can be a flat surface or a roughened surface.

[0085] The transparent conductive layer of the present invention is nickel-gold alloy (Ni/Au), indium tin oxide (Indium Tin Oxide; ITO), indium zinc oxide (Indium Zinc Oxide; IZO), indium tungsten oxide (Indium Tungsten Oxide; IWO), or Indium Gallium Oxide (IGO).

[0086] The substrate of the present invention can be sapphire (Al 2 O 3 ) Substrate, silicon carbide (SiC) substrate, lithium aluminate substrate (AlLiO 2 ), lithium gallate substrate (LiGaO 2 ), silicon (Si) substrate, gallium nitride (GaN) substrate, zinc oxide (ZnO) substrate, aluminum oxide zinc substrate (AlZnO), gallium arsenide (GaAs) substrate, gallium phosphide (GaP) substrate, gallium antimonide Substrate (GaSb), indium phosphide (InP) substrate, indium arsenide (InAs) substrate or zinc selenide (ZnSe) substrate.

[0087] The buffer layer of the present invention can be of gallium nitride (GaN), aluminum gallium nitride (AlGaN), aluminum nitride (AlN), or an InGaN/InGaN superlattice structure.

[0088] The light-emitting layer of the present invention has a single heterostructure, a double heterostructure, a single quantum well layer or a multiple quantum well layer structure.

[0089] The semiconductor layer of the present invention is Al x In y Ga 1-x-y N, where 0≤x≤1 and 0≤y≤1.

[0090] The pattern of the present invention is continuous or partially continuous.

[0091] The pattern of the present invention is a cylindrical hole, a polygonal columnar hole or a long strip hole.

[0092] The height of the continuous holes of the present invention is between 0.05 and 2.0 μm.

[0093] The width of the continuous holes of the present invention is between 0.1 and 10.0 μm.

[0094] The distance between the light-emitting layer of the present invention and the continuous hole is between 3.0 and 4.0 μm.

[0095] The distance between the light-emitting layer of the present invention and the surface of the p-type conducting layer is between 0.15 and 0.3 μm.

[0096] The present invention further includes KOH, H 2 SO 4 Or H 3 PO 4 The chemical etching solution etches the continuous hole surface to form a rough surface.

[0097] The method of the present invention to remove the patterned silicon dioxide layer is to use BOE chemical etching solution.

[0098] Please refer to Figure 4 , Is the method flow chart of the first manufacturing method of the present invention. Step 4-1, provide a substrate. The aforementioned substrate can be sapphire (Al 2 O 3 ) Substrate, silicon carbide (SiC) substrate, lithium aluminate substrate (AlLiO 2 ), lithium gallate substrate (LiGaO 2 ), silicon (Si) substrate, gallium nitride (GaN) substrate, zinc oxide (ZnO) substrate, aluminum oxide zinc substrate (AlZnO), gallium arsenide (GaAs) substrate, gallium phosphide (GaP) substrate, gallium antimonide Substrate (GaSb), indium phosphide (InP) substrate, indium arsenide (InAs) substrate or zinc selenide (ZnSe) substrate, generally use sapphire (Al 2 O 3 ) Substrate. Step 4-2, forming a patterned silicon dioxide layer on the substrate. The silicon dioxide material is deposited on the above-mentioned substrate by a chemical vapor deposition (CVD) or low-temperature sputtering (Sputtering) method to form a thin layer. Then a photoresist film is formed on the surface of the aforementioned silicon dioxide layer, and then the photoresist film is patterned by photolithography so that the expected etched part is exposed. Finally, a patterning process is performed by wet etching, dry etching, or inductively coupled plasma etcher (ICP) to obtain a patterned silicon dioxide layer. Step 4-3, forming a filling layer on the patterned silicon dioxide layer. First, a group III nitride filling layer is formed on the patterned silicon dioxide layer. Since the silicon dioxide layer belongs to the polycrystalline system, the III-nitride layer of the single crystal system cannot be directly epitaxially on the surface of the polycrystalline system, which causes a phenomenon of epitaxially lateral overgrowth (ELOG). During the epitaxy process, discontinuous voids are generated between the III nitride layer and the silicon dioxide layer. After the III-nitride material grown from the hole reaches the surface of the silicon dioxide layer, it grows laterally until it joins the III-nitride material at the other end to form a plane filling layer. The aforementioned filling layer can also be used as a buffer layer to improve the epitaxial quality of the semiconductor layer. Step 4-4, forming a semiconductor layer on the above-mentioned filling layer. The semiconductor light-emitting structure can be deposited on the aforementioned filling layer by techniques such as Metal Organic Chemical Vapor Deposition (MOCVD) or Molecular Beam Epitaxy (MBE). The aforementioned semiconductor layer includes an n-type conduction layer, a light-emitting layer, an electron blocking layer, and a p-type conduction layer. Step 4-5, after removing the patterned silicon dioxide layer, a continuous hole is formed between the substrate and the filling layer. The present invention uses a chemical wet etching method to remove the silicon dioxide layer. A chemical solution that can react with the oxide is selected and adjusted to an appropriate ratio, the silicon dioxide layer is immersed in the chemical solution, and the chemical solution and the silicon dioxide material are chemically reacted to remove the silicon dioxide layer. After the removal of the silicon dioxide layer is completed, the columnar III nitrides will remain connected to the aforementioned substrate. If the second etching solution is further used to etch the surface of the group III nitride to increase the irregularity of the surface, the luminous efficiency of the semiconductor layer can be improved. Step 4-6, etching the semiconductor layer to form a cutting platform. The photoresist is fully coated on the surface of the p-type conductive layer by a photoresist spin coater with centrifugal force to form a photoresist film. Then, the photoresist film is patterned by photolithography to form a mask, so that the expected etching portion is exposed. Then, a cutting platform is formed by wet etching, dry etching, or inductively coupled plasma etcher (ICP). Steps 4-7, forming a transparent conductive layer on the semiconductor layer. Generally, a transparent conductive layer is formed on the semiconductor layer by physical vapor deposition methods such as vapor deposition and sputtering. The material can be nickel/gold (Ni/Au), indium tin oxide (ITO), indium zinc oxide (IZO), indium tungsten oxide (IWO) or indium gallium oxide (Indium Gallium Oxide; IGO).

[0099] Figure 5 It is a method flow chart of the second manufacturing method of the present invention. Step 5-1, provide a substrate. The aforementioned substrate can be sapphire (Al 2 O 3 ) Substrate, silicon carbide (SiC) substrate, lithium aluminate substrate (AlLiO 2 ), lithium gallate substrate (LiGaO 2 ), silicon (Si) substrate, gallium nitride (GaN) substrate, zinc oxide (ZnO) substrate, aluminum oxide zinc substrate (AlZnO), gallium arsenide (GaAs) substrate, gallium phosphide (GaP) substrate, gallium antimonide Substrate (GaSb), indium phosphide (InP) substrate, indium arsenide (InAs) substrate or zinc selenide (ZnSe) substrate, generally use sapphire (Al 2 O 3 ) Substrate. Step 5-2, forming a buffer layer on the substrate. A buffer layer is formed on the substrate by using metal organic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE) techniques. Step 5-3, forming a patterned silicon dioxide layer on the buffer layer. The silicon dioxide material is deposited on the above-mentioned substrate by a chemical vapor deposition (CVD) or low-temperature sputtering (Sputtering) method to form a thin layer. Then a photoresist film is formed on the surface of the aforementioned silicon dioxide layer, and then the photoresist film is patterned by photolithography so that the expected etched part is exposed. Finally, a patterning process is performed by wet etching, dry etching, or inductively coupled plasma etcher (ICP) to obtain a patterned silicon dioxide layer. Step 5-4, forming a filling layer on the patterned silicon dioxide layer. First, a group III nitride filling layer is formed on the patterned silicon dioxide layer. Since the silicon dioxide layer belongs to the polycrystalline system, the III-nitride layer of the single crystal system cannot be directly epitaxially on the surface of the polycrystalline system, which causes a phenomenon of epitaxially lateral overgrowth (ELOG). After the III-nitride material grown from the hole reaches the surface of the silicon dioxide layer, it grows laterally until it joins the III-nitride material at the other end to form a plane filling layer. The aforementioned filling layer can also be used as a buffer layer to improve the epitaxial quality of the semiconductor layer. Step 5-5, a semiconductor layer is formed on the filling layer. The semiconductor light-emitting structure can be deposited on the aforementioned filling layer by a technique such as Metal Organic Chemical Vapor Deposition (MOCVD) or Molecular Beam Epitaxy (MBE). The aforementioned semiconductor layer includes an n-type conduction layer, a light-emitting layer, an electron blocking layer, and a p-type conduction layer. Step 5-6, after removing the patterned silicon dioxide layer, a continuous hole is formed between the buffer layer and the filling layer. The present invention uses a chemical wet etching method to remove the silicon dioxide layer. A chemical solution that can react with the oxide is selected and adjusted to an appropriate ratio, the silicon dioxide layer is immersed in the chemical solution, and the chemical solution and the silicon dioxide material are chemically reacted to remove the silicon dioxide layer. After the removal of the silicon dioxide layer is completed, the columnar group III nitride will be left between the buffer layer and the filling layer. If the second etching solution is further used to etch the surface of the group III nitride to increase the irregularity of the surface, the luminous efficiency of the semiconductor layer can be improved. Steps 5-7, etching the semiconductor layer to form a cutting platform. The photoresist is fully coated on the surface of the p-type conductive layer by a photoresist spin coater with centrifugal force to form a photoresist film. Then, the photoresist film is patterned by photolithography to form a mask, so that the expected etching portion is exposed. Then a cutting platform is formed by wet etching, dry etching, or inductively coupled plasma etcher (ICP). Steps 5-8, forming a transparent conductive layer on the semiconductor layer. Generally, a transparent conductive layer is formed on the semiconductor layer by physical vapor deposition methods such as vapor deposition and sputtering. The material can be nickel/gold (Ni/Au), indium tin oxide (ITO), indium zinc oxide (IZO), indium tungsten oxide (IWO) or indium gallium oxide (Indium Gallium Oxide; IGO).

[0100] After the above steps 4-7 and 5-8, according to the general light-emitting diode manufacturing process, a p-type electrode is formed on the transparent conductive layer and an n-type electrode on the n-type conductive layer. In addition, an insulating layer can be further formed to protect the semiconductor device.

[0101] The above-mentioned flow chart of the method of the present invention and its implementation content will be combined with the drawings and schematic diagrams of the structure of each step to introduce the structure of the present invention and the formation method of each step in detail.

[0102] The present invention first proposes the first manufacturing method. Please refer to Figure 6A As shown, the surface of the substrate is cleaned and a patterned silicon dioxide layer is formed on the aforementioned substrate. A substrate 601 is provided. The aforementioned substrate may be sapphire (Al 2 O 3 ) Substrate, silicon carbide (SiC) substrate, lithium aluminate substrate (AlLiO 2 ), lithium gallate substrate (LiGaO 2 ), silicon (Si) substrate, gallium nitride (GaN) substrate, zinc oxide (ZnO) substrate, aluminum oxide zinc substrate (AlZnO), gallium arsenide (GaAs) substrate, gallium phosphide (GaP) substrate, gallium antimonide Substrate (GaSb), indium phosphide (InP) substrate, indium arsenide (InAs) substrate or zinc selenide (ZnSe) substrate. The surface of the substrate is cleaned. For example: thermal cleaning (thermal cleaning) at 1200°C in a hydrogen-filled environment. Then, the silicon dioxide material is deposited on the aforementioned substrate 601 to form a thin layer 603 by using chemical vapor deposition (CVD) or low temperature sputtering (Sputtering). Next, a photoresist film is formed on the surface of the aforementioned silicon dioxide layer 603, and then the photoresist film is patterned by photolithography so that the expected etched part is exposed. Finally, a patterning process is performed by wet etching, dry etching or an inductively coupled plasma etcher (ICP) system to obtain a patterned silicon dioxide layer 603. The aforementioned patterned silicon dioxide layer 603 may be a continuous or partially continuous pattern. Please refer to Figure 10A~10D , Which is a schematic diagram of various patterns of the silicon dioxide layer. Such as Figure 10A Is a cylindrical groove pattern, Figure 10B It is a hexagonal cylindrical groove pattern, Figure 10C It is a quadrangular column groove pattern, Figure 10D It is a long strip groove pattern. In addition to the aforementioned patterns, other patterns are not limited. Aforementioned Figure 10A~Figure 10C Is a continuous pattern, and the aforementioned Figure 10D It is a partially continuous pattern.

[0103] Next, please refer to Figure 6B As shown, a III-nitride hole filling layer 605 is formed on the patterned silicon dioxide layer 603. The aforementioned hole filling layer can be regarded as a buffer layer. The silicon dioxide layer belongs to the polycrystalline system. Because the lattice mismatch is too high, the III-nitride layer of the single crystal system cannot be directly epitaxial on the surface of the polycrystalline system, resulting in an epitaxially lateral overgrowth (Epitaxially Lateral Overgrowth; ELOG) phenomenon. The present invention uses a chemical vapor deposition (Chemical Vapor Deposition; CVD) method to grow III-nitride material from the cavity 627. When it reaches the surface of the silicon dioxide layer 603, the foregoing III-nitride material will grow laterally The way until it is connected to the group III nitride at the other end to form a buffer layer plane. The aforementioned group III nitride hole filling layer 605 may be Al x In y Ga 1-x-y N, where 0≤x≤1 and 0≤y≤1.

[0104] Furthermore, please refer to Figure 6C As shown, a semiconductor layer 615 is formed on the aforementioned III-nitride hole filling layer 605. The aforementioned semiconductor layer 615 includes an n-type conduction layer 607, a light-emitting layer 609, an electron blocking layer 611, and a p-type conduction layer 613. The semiconductor layer 615 can be deposited on the III-nitride hole filling layer 605 by using metal organic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE) techniques. Firstly, Group IV atoms are doped to form an n-type conduction layer 607 on the III-nitride hole filling layer 605. In this embodiment, it is silicon atom (Si), and the precursor of silicon in the organometallic chemical vapor deposition machine can be silicon methane (SiH 4 ) Or silicon ethane (Si 2 H 6 ). The formation method of the n-type conductive layer 605 is from a high concentration of silicon atom (Si) doped gallium nitride layer (GaN) or an aluminum gallium nitride layer (AlGaN) to a low concentration of silicon atom (Si) doped Gallium nitride layer or aluminum gallium nitride layer (AlGaN). The gallium nitride layer (GaN) or aluminum gallium nitride layer (AlGaN) doped with silicon atoms (Si) at a high concentration can provide better conductivity between n-type electrodes.

[0105] Next, a light-emitting layer 609 is formed on the n-type conductive layer 607. The light emitting layer 609 may be a single heterostructure, a double heterostructure, a single quantum well layer or a multiple quantum well layer structure. Currently, a multiple quantum well layer structure, that is, a multiple quantum well layer/barrier layer structure, is mostly used. The quantum well layer may use indium gallium nitride (InGaN), and the barrier layer may use a ternary structure such as aluminum gallium nitride (AlGaN). In addition, a quaternary structure can also be used, that is, aluminum gallium indium nitride (Al x In y Ga 1-x-y N) At the same time as a quantum well layer and a barrier layer. The ratio of aluminum to indium is adjusted so that the energy level of the aluminum gallium indium nitride lattice can be a high-level barrier layer and a low-level quantum well layer, respectively. The light-emitting layer 609 may be doped with n-type or p-type dopants, it may be doped with both n-type and p-type dopants, or it may be completely undoped. In addition, the quantum well layer may be doped and the barrier layer is not doped, the quantum well layer is not doped and the barrier layer is doped, the quantum well layer and the barrier layer are both doped, or the quantum well layer and the barrier layer are not doped. Furthermore, high-concentration doping (delta doping) may be performed in a partial region of the quantum well layer.

[0106] After that, a p-type conductive electron blocking layer 611 is formed on the light-emitting layer 609. The p-type conductive electron blocking layer 611 includes a first type III-V semiconductor layer and a second type III-V semiconductor layer. The energy gaps of these two III-V semiconductor layers are different, and they are periodically repeatedly deposited on the light-emitting layer 609. The previous periodic repeating of the deposition action can form an electron blocking layer with a higher energy barrier (the energy barrier is higher than The energy barrier of the active light-emitting layer is used to prevent excessive electrons (e-) from overflowing the light-emitting layer 609. The foregoing first III-V semiconductor layer can be aluminum indium gallium nitride (Al x In y Ga 1-x-y N) layer, the foregoing second III-V group semiconductor layer may be aluminum indium gallium nitride (Al u In v Ga 1-u-v N) Layer. Among them, 0 <1, x+y≦1, 0≦u<1, 0≦v≦1, and u+v≦1. When x=u, y≠v. In addition, the aforementioned III-V semiconductor layer may also be gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), nitrogen Aluminum indium (AlInN).

[0107] Finally, the group 2 atoms are doped to form a p-type conductive layer 613 on the electron blocking layer 611. In this embodiment, it is a magnesium atom. The precursor of magnesium can be CP in the organometallic chemical vapor deposition machine. 2 Mg. The p-type conductive layer 613 is formed in order from a low concentration of magnesium doped with gallium nitride (GaN) or aluminum gallium nitride (AlGaN) to a high concentration of magnesium doped (Mg) with nitrogen. The gallium oxide layer or the aluminum gallium nitride layer (AlGaN). The gallium nitride layer (GaN) or aluminum gallium nitride layer doped with magnesium atoms (Mg) at a high concentration can provide better conductivity between the p-type electrodes.

[0108] by Figure 6D As shown, the aforementioned silicon dioxide layer is removed by wet etching to form continuous holes 617. Through the selection and preparation of chemical solutions, the silicon dioxide layer 603 is immersed in the aforementioned chemical solution, and the chemical reaction between the aforementioned chemical solution and the aforementioned silicon dioxide layer is accelerated by means of ultrasonic vibration and UV irradiation to increase the temperature of the solution. The temperature of the aforementioned chemical solution is as high as about 150°C. The aforesaid chemical solution can be Buffer Oxide Etcher (BOE), which mainly etches silicon dioxide (Silicon Dioxide; SiO2) or silicon nitride (Silicon Nitride; Si3N4). The aforementioned buffered oxidation etching solution is fluorinated amine (NH 4 F) The mixed solution of solution and hydrofluoric acid (HF), the preparation method can be about 40% by weight of fluorinated amine (NH 4 F) The solution is then mixed with a hydrofluoric acid (HF) solution with a concentration of about 49% to prepare a buffered oxidation etching solution of about 10% by volume. In more detail, take out the transparent granular fluorinated amine (NH 4 F) About 90 grams of solids are poured into about 135 ml of deionized water and stirred to melt. Take out about 180ml of fluorinated amine (NH 4 F) The solution is poured into a container, and about 20 ml of about 49% hydrofluoric acid (HF) solution is added to the aforementioned container and mixed together until uniform to complete the preparation of the buffered oxidation etching solution. The silicon dioxide layer 603 is briefly immersed in the etching solution, and finally, after the silicon dioxide layer 603 is eroded, a continuous hole 617 is left between the substrate 601 and the hole filling layer 605.

[0109] Please refer to Figure 6E As shown, a transparent conductive layer is first formed on the semiconductor layer, and then the cutting platform is etched to expose the n-type conductive layer. Generally, the transparent conductive layer 619 is formed on the semiconductor layer 615 by a physical vapor deposition method such as vapor deposition or sputtering. The material can be nickel/gold (Ni/Au), indium tin oxide (ITO), indium zinc oxide (IZO), indium tungsten oxide (IWO) or indium gallium oxide (Indium gallium oxide). Gallium Oxide; IGO). Then, the photoresist is completely coated on the surface of the transparent conductive layer 619 by a photoresist spin coater with centrifugal force to form a photoresist film. Then, the photoresist film is patterned by photolithography to form a mask, so that the expected etching portion is exposed. Then the mesa process is performed by wet etching, dry etching or inductively coupled plasma etcher (ICP). The aforementioned mesa process is to etch the semiconductor layer 615 to form the cutting platform 631 while exposing the n-type conductive layer 607.

[0110] Please refer to Figure 6F As shown, an n-type electrode is formed on the n-type conductive layer, and a p-type electrode is formed on the transparent conductive layer. The n-type electrode 623 and the p-type electrode 621 can be deposited on the n-type conductive layer 607 and the transparent conductive layer 619 by using physical vapor deposition methods such as sputtering and evaporation. The n-type electrode 623 may be titanium/aluminum/titanium/gold (Ti/Al/Ti/Au), chromium-gold alloy (Cr/Au) or lead-gold alloy (Pd/Au), and the p-type electrode 621 may be nickel Gold alloy (Ni/Au), platinum alloy (Pt/Au), tungsten (W), chromium gold alloy (Cr/Au) or palladium (Pd).

[0111] Finally, such as Figure 6G As shown, an insulating layer 625 can be formed to cover the outer layer of the semiconductor device and expose the n-type electrode 623 and the p-type electrode 621. The aforementioned insulating layer can be silicon dioxide (SiO 2 ), epoxy resin (Epoxy), silicon nitride (Si 3 N 4 ), titanium dioxide (TiO 2 ) Or aluminum nitride (AlN).

[0112] In addition, Figure 6F versus Figure 6F’ as well as Figure 6G versus Figure 6G’ The difference lies in the roughened surface of the p-type conductive layer 613. when Figure 6D After the silicon dioxide layer is de-patterned, the surface of the p-type conductive layer 613 is first etched by wet etching, dry etching, or inductively coupled plasma etcher (ICP) to etch the irregular surface, and then proceed Figure 6E with Figure 6F Manufacturing process.

[0113] In addition to the first manufacturing method of the present invention, there are Figure 6F , Figure 6F’ , Figure 6G and Figure 6G’ In addition to the four structures, several other structures can be derived, such as Figure 7A , Figure 7A’ , Figure 7B as well as Figure 7B’. The difference in its manufacturing method is Figure 6D The completion of the removal of the silicon dioxide layer to form a continuous hole 617 is regarded as the first etching, and then the plurality of holes 617 that have been formed are added one more wet etching and regarded as the second etching. The second etching is mainly to form a rough surface on the surface of the hole filling layer, thereby increasing the light extraction efficiency of the semiconductor optoelectronic device. The second etching is to infiltrate the chemical solution into the structure through the continuous holes 617 to erode the surface of the III-nitride hole filling layer 605 to form a rough surface. The chemical solution can be potassium hydroxide (Potassium Hydroxide; KOH), sulfuric acid (Sulfuric Acid; H 2 SO 4 ) Or phosphoric acid (Phosphoric Acid; H 3 PO 4 ). In the second etching process, ultrasonic vibration and UV irradiation are used to increase the temperature of the solution to increase the chemical reaction rate between the aforementioned chemical solution and the aforementioned group III nitride. Note that the etching time is completed within a few seconds. The subsequent process steps and Figure 6E and Figure 6F The same, so I won’t repeat them here.

[0114] The present invention further provides a second manufacturing method. The main difference from the first method is that continuous holes are formed between the buffer layers. Please refer to Figure 8A , Forming a buffer layer on a substrate, and then patterning the silicon dioxide layer. A substrate 801 is provided. The aforementioned substrate may be sapphire (Al 2 O 3 ) Substrate, silicon carbide (SiC) substrate, lithium aluminate substrate (AlLiO 2 ), lithium gallate substrate (LiGaO 2 ), silicon (Si) substrate, gallium nitride (GaN) substrate, zinc oxide (ZnO) substrate, aluminum oxide zinc substrate (AlZnO), gallium arsenide (GaAs) substrate, gallium phosphide (GaP) substrate, gallium antimonide Substrate (GaSb), indium phosphide (InP) substrate, indium arsenide (InAs) substrate or zinc selenide (ZnSe) substrate. The surface of the substrate is cleaned. For example: thermal cleaning (thermal cleaning) at 1200°C in a hydrogen-filled environment. Then, a buffer layer 803 is formed on the aforementioned substrate 801 by using metal organic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE) techniques. The aforementioned buffer layer can be Al x In y Ga 1-x-y N, where 0≤x≤1 and 0≤y≤1.

[0115] Then, the silicon dioxide material is deposited on the buffer layer 803 to form a thin layer by using chemical vapor deposition (CVD) or low temperature sputtering (Sputtering). Although the number of lattice mismatches between group III nitrides and silicon dioxide is very high, because the lattice arrangement of group III nitrides is more orderly than that of silicon dioxide, silicon dioxide can form a thin film layer on the group III nitrides. Be rejected. Next, a photoresist film is formed on the surface of the aforementioned silicon dioxide layer 805, and then the photoresist film is patterned by photolithography so that the expected etched part is exposed. Finally, a patterning process is performed by wet etching, dry etching, or inductively coupled plasma etcher (ICP) to obtain a patterned silicon dioxide layer. The aforementioned patterned silicon dioxide layer 805 may be a continuous or partially continuous pattern. Please refer to Figure 10A~Figure 10D , Which is a schematic diagram of various patterns of the silicon dioxide layer. Such as Figure 10A Is a cylindrical groove pattern, Figure 10B It is a hexagonal cylindrical groove pattern, Figure 10C It is a quadrangular column groove pattern, Figure 10D It is a long strip groove pattern. In addition to the aforementioned patterns, other patterns are not limited. Aforementioned Figure 10A~Figure 10C Is a continuous pattern, and the aforementioned Figure 10D The picture shows a partially continuous pattern.

[0116] Next, please refer to Figure 8B As shown, a III-nitride hole filling layer is formed on the patterned silicon dioxide layer. The aforementioned hole filling layer 807 can be regarded as a buffer layer. The silicon dioxide layer 805 belongs to the polycrystalline system. Due to the high number of lattice mismatches, the III-nitride layer of the single crystal system cannot be directly epitaxial on the surface of the polycrystalline system, resulting in a kind of epitaxially lateral overgrowth (Epitaxially Lateral Overgrowth; ELOG) phenomenon. The present invention uses a chemical vapor deposition (Chemical Vapor Deposition; CVD) method to grow III-nitride material from the cavity 833, and when it reaches the surface of the silicon dioxide layer 805, the foregoing III-nitride material will grow laterally The way until it is connected to the group III nitride at the other end to form a buffer layer 807 plane. The aforementioned group III nitride hole filling layer 807 may be Al x In y Ga 1-x-y N, where 0≤x≤1 and 0≤y≤1.

[0117] Please refer to Figure 8C As shown, a semiconductor layer is formed on the III-nitride hole filling layer. A semiconductor layer 819 is formed on the aforementioned III-nitride hole filling layer 807. The aforementioned semiconductor layer 819 includes an n-type conduction layer 811, a light-emitting layer 813, an electron blocking layer 815, and a p-type conduction layer 817. The semiconductor layer 819 may be deposited on the III-nitride hole filling layer 807 by using metal organic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE) techniques. Firstly, atoms of Group IV are doped to form an n-type conductive layer 811 on the III-nitride hole filling layer 807. In this embodiment, it is silicon atom (Si), and the precursor of silicon in the organometallic chemical vapor deposition machine can be silicon methane (SiH 4 ) Or silicon ethane (Si 2 H 6 ). The formation of the n-type conductive layer 811 is from a high concentration of silicon atom (Si) doped gallium nitride layer (GaN) or an aluminum gallium nitride layer (AlGaN) to a low concentration doped silicon atom (Si). Gallium nitride layer or aluminum gallium nitride layer (AlGaN). The gallium nitride layer (GaN) or aluminum gallium nitride layer (AlGaN) doped with silicon atoms (Si) at a high concentration can provide better conductivity between n-type electrodes.

[0118] Next, a light-emitting layer 813 is formed on the n-type conductive layer 811. The light emitting layer 813 may be a single heterostructure, a double heterostructure, a single quantum well layer or a multiple quantum well layer structure. Currently, a multiple quantum well layer structure, that is, a multiple quantum well layer/barrier layer structure, is mostly used. The quantum well layer may use indium gallium nitride (InGaN), and the barrier layer may use a ternary structure such as aluminum gallium nitride (AlGaN). In addition, a quaternary structure can also be used, that is, aluminum gallium indium nitride (Al x In y Ga 1-x-y N) At the same time as a quantum well layer and a barrier layer. The ratio of aluminum to indium is adjusted so that the energy level of the aluminum gallium indium nitride lattice can be a high-level barrier layer and a low-level quantum well layer, respectively. The light-emitting layer 813 may be doped with n-type or p-type dopants, may be doped with both n-type and p-type dopants, or may be completely undoped. In addition, the quantum well layer may be doped and the barrier layer is not doped, the quantum well layer is not doped and the barrier layer is doped, the quantum well layer and the barrier layer are both doped, or the quantum well layer and the barrier layer are not doped. Furthermore, high-concentration doping (delta doping) may be performed in a partial region of the quantum well layer.

[0119] After that, a p-type conductive electron blocking layer 815 is formed on the light-emitting layer 813. The p-type conductive electron blocking layer 815 includes a first type III-V semiconductor layer and a second type III-V semiconductor layer. The energy gaps of these two III-V semiconductor layers are different, and they are periodically and repeatedly deposited on the light-emitting layer 813. The previous periodic and repeated deposition actions can form an electron blocking layer with a higher energy barrier (the energy barrier is higher than The energy barrier of the active light-emitting layer) to prevent excessive electrons (e-) from overflowing the light-emitting layer 813. The foregoing first III-V semiconductor layer can be aluminum indium gallium nitride (Al x In y Ga 1-x-y N) layer, the foregoing second III-V group semiconductor layer may be aluminum indium gallium nitride (Al u In v Ga 1-u-v N) Layer. Among them, 0 <1, x+y≦1, 0≦u<1, 0≦v≦1, and u+v≦1. When x=u, y≠v. In addition, the aforementioned III-V semiconductor layer may also be gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), nitrogen Aluminum indium (AlInN).

[0120] Finally, the group 2 atoms are doped to form a p-type conductive layer 817 on the electron blocking layer 815. In this embodiment, it is a magnesium atom. The precursor of magnesium can be CP in the organometallic chemical vapor deposition machine. 2 Mg. The p-type conductive layer 817 is formed in order from a low concentration of magnesium doped (Mg) gallium nitride layer (GaN) or an aluminum gallium nitride layer (AlGaN) to a high concentration of nitrogen doped with magnesium atoms (Mg) The gallium oxide layer or the aluminum gallium nitride layer (AlGaN). The gallium nitride layer (GaN) or aluminum gallium nitride layer doped with magnesium atoms (Mg) at a high concentration can provide better conductivity between the p-type electrodes.

[0121] Next, please refer to Figure 8D As shown, the aforementioned silicon dioxide layer is removed by wet etching to form continuous holes. Through the selection and preparation of the chemical solution, the silicon dioxide layer 805 is immersed in the aforementioned chemical solution, and the chemical reaction between the aforementioned chemical solution and the aforementioned silicon dioxide layer is accelerated by means of ultrasonic vibration and UV irradiation to increase the temperature of the solution. The temperature of the aforementioned chemical solution is as high as about 150°C. The aforesaid chemical solution can choose Buffer Oxide Etcher (BOE), which mainly etches silicon dioxide (Silicon Dioxide; SiO 2 ) Or silicon nitride (Silicon Nitride; Si 3 N 4 ). The aforementioned buffered oxidation etching solution is fluorinated amine (NH 4 F) The mixed solution of solution and hydrofluoric acid (HF), the preparation method can be about 40% by weight of fluorinated amine (NH 4 F) The solution is then mixed with a hydrofluoric acid (HF) solution with a concentration of about 49% to prepare a buffered oxidation etching solution of about 10% by volume. In more detail, take out the transparent granular fluorinated amine (NH 4 F) About 90 grams of solids are poured into about 135 ml of deionized water and stirred to melt. Take out about 180ml of fluorinated amine (NH 4 F) The solution is poured into a container, and about 20 ml of about 49% hydrofluoric acid (HF) solution is added to the aforementioned container and mixed together until uniform to complete the preparation of the buffered oxidation etching solution. The silicon dioxide 805 is briefly immersed in the aforementioned etching solution, and finally, after the silicon dioxide layer 805 is eroded, continuous holes 821 are left between the buffer layer 803 and the hole filling layer 807.

[0122] Please refer to Figure 8E As shown, a transparent conductive layer is first formed on the semiconductor layer, and then the cutting platform is etched to expose the n-type conductive layer. Generally, the transparent conductive layer 823 is formed on the semiconductor layer 819 by physical vapor deposition methods such as vapor deposition and sputtering. The material can be nickel/gold (Ni/Au), indium tin oxide (ITO), indium zinc oxide (IZO), indium tungsten oxide (IWO) or indium gallium oxide (Indium gallium oxide). Gallium Oxide; IGO). Then, the photoresist is completely coated on the surface of the transparent conductive layer 823 by a photoresist spin coater with centrifugal force to form a photoresist film. Then, the photoresist film is patterned by photolithography to form a mask, so that the expected etching portion is exposed. Then the mesa process is performed by wet etching, dry etching or inductively coupled plasma etcher (ICP). The aforementioned mesa process is to etch the semiconductor layer 819 to form a cutting platform 825 while exposing the n-type conductive layer 811.

[0123] Please refer to Figure 8F As shown, an n-type electrode is formed on the n-type conductive layer, and a p-type electrode is formed on the transparent conductive layer. The n-type electrode 829 and the p-type electrode 827 can be deposited on the n-type conductive layer 811 and the transparent conductive layer 823 by using physical vapor deposition methods such as sputtering and vapor deposition. The n-type electrode 829 may be titanium/aluminum/titanium/gold (Ti/Al/Ti/Au), chromium-gold alloy (Cr/Au) or lead-gold alloy (Pd/Au), and the p-type electrode 827 may be nickel Gold alloy (Ni/Au), platinum alloy (Pt/Au), tungsten (W), chromium gold alloy (Cr/Au) or palladium (Pd).

[0124] Finally, such as Figure 8G As shown, an insulating layer 831 can be formed to cover the outer layer of the semiconductor device to expose the n-type electrode 829 and the p-type electrode 827. The aforementioned insulating layer can be silicon dioxide (SiO 2 ), epoxy resin (Epoxy), silicon nitride (Si 3 N 4 ), titanium dioxide (TiO 2 ) Or aluminum nitride (AlN).

[0125] In addition, Figure 8F versus Figure 8F’ as well as Figure 8G versus Figure 8G’ The difference lies in the roughened surface of the p-type conductive layer 817. when Figure 8D After the silicon dioxide layer is de-patterned, the surface of the p-type conductive layer 817 is first etched out of the irregular surface by wet etching, dry etching or inductively coupled plasma etcher (ICP). Figure 8E with Figure 8F Manufacturing process.

[0126] In addition to the second manufacturing method of the present invention, there are Figure 8F , Figure 8F’ , Figure 8G and Figure 8G’ In addition to the four structures, several other structures can be derived, such as Figure 9A , Figure 9A’ , Figure 9B as well as Figure 9B’. The difference in its manufacturing method is Figure 8D The completion of removing the silicon dioxide layer 805 to form the continuous hole 821 is regarded as the first etching, and then the plurality of holes 821 that have been formed are added one more wet etching and regarded as the second etching. The second etching is mainly to form a rough surface on the surface of the buffer layer 803 and the hole filling layer 807, so as to increase the light emitting efficiency of the light emitting diode. The second etching is to infiltrate the chemical solution into the structure through continuous holes 821 to erode the surface of the III-nitride buffer layer 803 and the hole filling layer 807 to form a rough surface. The chemical solution can be potassium hydroxide (PotassiumHydroxide; KOH), sulfuric acid (Sulfuric Acid; H 2 SO 4 ) Or phosphoric acid (Phosphoric Acid; H 3 PO 4 ). In the second etching process, ultrasonic vibration and UV irradiation are used to increase the temperature of the solution to increase the chemical reaction rate between the aforementioned chemical solution and the aforementioned group III nitride. Note that the etching time is completed within a few seconds. The subsequent process steps and Figure 8E and Figure 8F the same.

[0127] For the continuous holes formed by the above steps, please refer to Figure 9C As shown, the hole height 901 is between 0.05 and 2.0 μm, and the hole width 903 is between 0.1 and 10.0 μm. The distance 905 between the light-emitting layer and the continuous hole is about 3.0-4.0 μm, which helps the light generated by the light-emitting layer reflect through the continuous hole surface and increase the light intensity of the light-emitting surface. The distance 907 between the light-emitting layer and the surface of the p-type conductive layer is between 0.15-0.3 μm, which can help the light generated from the light-emitting layer to be emitted to the light-emitting surface.

[0128] Obviously, according to the description in the above embodiment, the present invention may have many modifications and differences. Therefore, it needs to be understood within the scope of the appended claims. In addition to the above detailed description, the present invention can also be widely implemented in other embodiments. The above are only preferred embodiments of the present invention, and are not used to limit the claims of the present invention; all other equivalent changes or modifications made without departing from the spirit of the present invention should be included in the appended claims Inside.