Low power consumption scanning test circuit and operation method

A scanning test, low power consumption technology, applied in the direction of measuring electricity, measuring electrical variables, measuring devices, etc., to ensure normal operation and reduce dynamic power consumption

Inactive Publication Date: 2011-02-16
SHANGHAI UNIVERSITY OF ELECTRIC POWER
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0013] The present invention aims at the problem that the combinatorial logic generates a large amount of useless power consumption in the current low-power scan test structure, and proposes a low-power scan te

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  • Low power consumption scanning test circuit and operation method
  • Low power consumption scanning test circuit and operation method

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Embodiment Construction

[0029] image 3 The block diagram of the low-power scan test structure is shown. During the process of moving the test vector in and the test result out of the scan chain, the data output from the scan flip-flop to the combinatorial logic remains logic '0', thereby greatly reducing power consumption.

[0030] image 3 Among them, SDFF1, SDFF2, ..., SDFFn are low-power scan flip-flops, SI is the scan input terminal, SE is the scan control terminal ('0' is the normal working mode, '1' is the scan test mode), CK is Scanning clocks, D1, D2, ..., Dn are output signals of the combinational logic, Q1, Q2, ..., Qn are signals output from the scan flip-flops to the combinational logic. Different from the traditional scan structure, the scan input (SD) of each scan flip-flop is connected to the SQ end of the previous scan flip-flop. During the scan shifting process of the test vector from SDFF1 to SDFFn and the process of moving the test result out of the scan chain, the output Q term...

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Abstract

The invention relates to a lower power consumption scanning test circuit and an operation method. On the basis of the traditional scanning trigger, a simple 2-input NOR-logic door is added and the structure of a scanning chain is improved slightly, the scanning input end SD of each power consumption scanning trigger is connected to the SQ end of the last power consumption scanning trigger, so that a combined logic part has no dynamic jumping power consumption in the process that a test vector moves in by scanning and the test result moves out by scanning, the test power consumption is greatly reduced and less hardware expenditure is needed. The invention provides the support for the development of the integrated circuit process and design technology and ensures normal work of the system chip.

Description

technical field [0001] The invention relates to a low power consumption integrated circuit, in particular to a low power consumption scanning test circuit. Background technique [0002] With the development of integrated circuit technology and design technology, integrated circuits have developed into the era of system-on-chip (SoC) and network-on-chip (NoC), and the operating frequency of chips is getting higher and higher, and the problem of power consumption during chip testing is becoming more and more serious. Since there is a great correlation between the input data when the chip is working normally, but the correlation between the input data is very low during the test, the activity of the circuit in the test mode is much higher than the normal working mode, so that the chip is under test. The power consumption in the mode is about 1-2 times higher than that in the normal mode. High power consumption during testing will reduce the battery life of handheld electronic ...

Claims

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Application Information

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IPC IPC(8): G01R31/3183
Inventor 叶波
Owner SHANGHAI UNIVERSITY OF ELECTRIC POWER
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