Low power consumption scanning test circuit and operation method

Abstract

The invention relates to a lower power consumption scanning test circuit and an operation method. On the basis of the traditional scanning trigger, a simple 2-input NOR-logic door is added and the structure of a scanning chain is improved slightly, the scanning input end SD of each power consumption scanning trigger is connected to the SQ end of the last power consumption scanning trigger, so that a combined logic part has no dynamic jumping power consumption in the process that a test vector moves in by scanning and the test result moves out by scanning, the test power consumption is greatly reduced and less hardware expenditure is needed. The invention provides the support for the development of the integrated circuit process and design technology and ensures normal work of the system chip.

Description

technical field [0001] The invention relates to a low power consumption integrated circuit, in particular to a low power consumption scanning test circuit. Background technique [0002] With the development of integrated circuit technology and design technology, integrated circuits have developed into the era of system-on-chip (SoC) and network-on-chip (NoC), and the operating frequency of chips is getting higher and higher, and the problem of power consumption during chip testing is becoming more and more serious. Since there is a great correlation between the input data when the chip is working normally, but the correlation between the input data is very low during the test, the activity of the circuit in the test mode is much higher than the normal working mode, so that the chip is under test. The power consumption in the mode is about 1-2 times higher than that in the normal mode. High power consumption during testing will reduce the battery life of handheld electronic ...

AI Technical Summary

Problems solved by technology

[0013] The present invention aims at the problem that the combinatorial logic generates a large amount of useless power consumption in the current low-power scan test structure, and proposes a low-power scan test circuit structure and operation method, which can eliminate the useless power consumption generated by the combinatorial logic, thereby reducing the overall Power consumption of integrated circuit chip test

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