Data readout circuit and readout method of phase-change storage unit

Abstract

The invention provides data readout circuit and readout method of a phase-change storage unit. The circuit at least comprises a read-current supply circuit, a judging pipe, a bias-voltage generation circuit, a pre-charging circuit, a comparison circuit, a discharging circuit and the like, wherein firstly the bit line of the phase-change storage unit to be read is pre-charged by the pre-charging circuit, the judging pipe can enter a conducting or cutoff state due to different resistance values of the phase-change storage unit to be read after charging is stopped, then the comparison circuit is used for comparing the voltage output when the judging pipe is conducting or cutoff with a preset reference voltage to output an electric potential corresponding to the resistance value of the phase-change storage unit to be read, and the discharging circuit is used for discharging the residual charge on the bit line after the corresponding electric potential is output by the comparison circuit, to finish data reading. The method can effectively avoid the influence of parasitic capacitance on the bit line.

Description

technical field [0001] The invention relates to a data readout circuit and a readout method, in particular to a data readout circuit and a readout method of a phase change memory unit. Background technique [0002] Phase change memory is a memory based on Ovshinsky electronic effect proposed by Ovshinsky in the late 1960s. It generally refers to chalcogenide random access memory, also known as Ovshinsky electric effect unified memory. The principle is to use the different resistance states of phase change materials processed to nanometer size in polycrystalline state (material in low resistance state) and amorphous state (material in high resistance state) to realize data storage. As a new type of memory, phase change memory is considered by the industry to be the most promising due to its fast read and write speed, high rewritable durability, long information retention time, high storage density, low read and write power consumption, and non-volatility. Potential next-gene...

AI Technical Summary

Problems solved by technology

However, in an actual phase change memory, on the one hand, due to the parasitic capacitance on the bit line, it takes a long time to operate the read current (voltage) that meets the above requirements

The read circuit needs to wait for the read current (voltage) to charge the bit line capacitance before it can correctly read the state of the phase change memory cell, which greatly restricts the speed characteristics of the phase change memory

On the other hand, due to the limitation of the carrier breakdown threshold inside the phase change unit, usually the carrier breakdown threshold is a very low voltage value, so that when the phase change unit is in high resistance and low resistance, its bit line The voltage difference is not very significant (less than the carrier breakdown threshold), making the reliability of the read data a serious problem

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