Looking for breakthrough ideas for innovation challenges? Try Patsnap Eureka!

Semiconductor structure and manufacturing method thereof

A manufacturing method and semiconductor technology, applied in the direction of semiconductor devices, semiconductor/solid-state device parts, electric solid-state devices, etc., can solve problems such as hindering chip heat conduction, low heat conduction efficiency, and affecting the reliability of stacked chip packaging structures, etc., to achieve Effect of improving heat dissipation efficiency and improving bonding strength

Active Publication Date: 2012-08-29
ADVANCED SEMICON ENG INC
View PDF0 Cites 0 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] However, in the known chip manufacturing process, the surface of the chip is covered with a protective layer, which has low heat conduction efficiency and will prevent the heat inside the chip from being conducted to the outside.
Even if a heat sink is installed on the lower chip of the stacked chip package structure, this protective layer will also hinder the heat conduction between the lower chip and the heat sink, thus affecting the reliability of the stacked chip package structure

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Semiconductor structure and manufacturing method thereof
  • Semiconductor structure and manufacturing method thereof
  • Semiconductor structure and manufacturing method thereof

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0058] figure 1 A semiconductor structure according to an embodiment of the invention is shown. Such as figure 1As shown, the semiconductor structure 100 includes a first chip 110 , wherein the first chip 110 has a plurality of TSVs 112 inside. A first wiring layer 120 is disposed on the active surface 110 a of the first chip 110 . Here, the first wiring layer 120 includes a first interconnection 122 , which is, for example, an interconnection formed in a back end of line (BEOL) process in the wafer fabrication process. The first interconnection 122 is, for example, connected between one end 112 a of the TSV 112 and the second conductive bump 184 under the first chip 110 . In addition, there may be other active or passive components (not shown) in the first chip 110 , so the first interconnection 122 may also be connected to these active or passive components.

[0059] The second wiring layer 130 is disposed on the back surface 110 b of the first chip 110 . The second wir...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

The invention discloses a semiconductor structure and a manufacturing method. In the semiconductor structure, conductive through holes and a radiation layer are arranged on the periphery of the back side of a lower chip for improving the bonding strength of a radiation fin assembled subsequently and for providing a good heat conducting path for improving the radiation efficiency of the semiconductor structure. The invention also provides a manufacturing method of the semiconductor structure.

Description

technical field [0001] The invention relates to a semiconductor structure and a manufacturing method thereof, and in particular to a semiconductor structure using through-silicon vias for chip stacking and a manufacturing method thereof. Background technique [0002] In today's information society, users are pursuing high-speed, high-quality, and multi-functional electronic products. As far as product appearance is concerned, the design of electronic products is moving towards the trend of light, thin, short and small. Therefore, electronic packaging technology has developed multi-chip packaging technologies such as stacked chip packaging. [0003] Stacked chip packaging is to package multiple integrated circuit (Integrated Circuit, IC) chips in the same packaging structure by vertical stacking, so that the packaging density can be increased to miniaturize the packaging structure, and the chip can be shortened by using three-dimensional stacking. The length of the signal t...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Patents(China)
IPC IPC(8): H01L23/367
CPCH01L2224/73253H01L2924/15311H01L2224/16145H01L2924/16235H01L2225/06568H01L2224/73204H01L2224/16225H01L2224/32225H01L2924/00
Inventor 王盟仁
Owner ADVANCED SEMICON ENG INC
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Patsnap Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Patsnap Eureka Blog
Learn More
PatSnap group products