Method and device for outputting base station master clock

Abstract

The invention discloses a method and device for outputting base station master clock; the method comprises the following steps: selecting parameters of multiple groups of loop filters for the loop filters in a digital phase-locked loop; calculating the jitter value of the output clock of the digital phase-locked loop when the loop filters in the digital phase-locked loop work under the parameter of each group of the loop filters; choosing the parameters of one group of the loop filters, corresponding to the minimum jitter value, as the selected working parameters of the loop filters in the digital phase-locked loop; and when the loop filters in the digital phase-locked loop work under the selected working parameters, taking the output clock of the digital phase-locked loop as the base station master clock. In the technical proposal, the phase noise and jittering of the base station master clock can be reduced.

Description

technical field [0001] The invention relates to the technical field of mobile communication, in particular to a method and a device for outputting a master clock of a base station. Background technique [0002] In Time Division Multiplexing Synchronous Code Division Multiple Access (TD-SCDMA, Time Division Synchronous CDMA) system and TD-LTE (that is, the long-term evolution of TD-SCDMA) system, the base station is based on the Global Positioning System (GPS, Global Position System) or other A synchronous clock source is used to adjust the clock output by the Oven Controlled Crystal Oscillator (OCXO, Oven Controlled Crystal Oscillator) and the digital phase-locked loop, and this clock is used as the baseband unit (BBU, Baseband Unit) system master clock, referred to here as Base station master clock. The main clock of the base station will generate TD_SCDMA\TD-LTE system frame timing signal, time slot timing and other synchronization signals, which will be distributed to ot...

AI Technical Summary

Problems solved by technology

However, there are differences in OCXO in different environments, and the high-frequency and low-frequency phase noise of the digital phase-locked loop has uncertainty. Therefore, when the phase noise is large, it will affect the output of the main system clock, making the local 61.44MHz clock deterioration

Especially when TD_SCDMA is compatible with the TD-LTE system, due to the poor clock quality, the data with high transmission rate has a high bit error rate, so that the bandwidth index of TD-LTE transmission cannot be completed

[0005] To sum up, the existing scheme of outputting the base station master clock has relatively large phase noise and jitter of the base station master clock output

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