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Method for establishing space correlation model of technical error in integrated circuit chip

A technology of spatial correlation and process deviation, applied in electrical digital data processing, special data processing applications, instruments, etc., can solve the problem that the accuracy of extraction results will be seriously affected, and the interference of pure random parts and measurement errors are not considered.

Active Publication Date: 2011-03-30
FUDAN UNIV
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Problems solved by technology

But this method has the following two disadvantages: (1) it is carried out for a single test chip, and the extraction result is a plurality of discrete spatial correlation functions
(2) It does not consider the pure random part of the on-chip deviation and the interference of measurement errors during the extraction process, and the accuracy of the extraction results will be seriously affected

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  • Method for establishing space correlation model of technical error in integrated circuit chip
  • Method for establishing space correlation model of technical error in integrated circuit chip
  • Method for establishing space correlation model of technical error in integrated circuit chip

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Embodiment Construction

[0085] The present invention is further illustrated below by specific implementation examples:

[0086] The present invention utilizes computer simulations to generate pseudo-measurement data. Pseudo-measurement data representing process variation mainly consists of four components: the spatially correlated part of intra-die variation, the purely random part of intra-die variation, the inter-die variation, and the measurement error.

[0087] The spatial correlation part of the intra-chip deviation is the most important component in the measurement data, and its correlation function is the spatial correlation function that reflects the spatial correlation of the intra-chip deviation. This part of the deviation can be simulated by a Gaussian random field [3, 4]. In the implementation example of the present invention, a method based on Cholesky decomposition is used to generate random fields [5]. The specific steps are as follows: First, according to a certain sampling strategy...

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Abstract

The invention belongs to the field of integrated circuits, relating to a method for establishing a space correlation model of technical errors in an integrated circuit chip. The method comprises the following steps of: extracting an unknown parameter of a space correlation function by utilizing the maximum likelihood estimation of a multi-test chip, and establishing the space correlation model ofthe errors in the chip; and multiplying a likelihood function of all test chips to obtain a joint likelihood function, solving through maximizing the joint likelihood function to obtain the space correlation function which is determined by a parameter value and can be directly used for circuit analysis design of the technical errors. The influence of pure random part of the error in the chip and the measurement error can be processed in the extraction process of the space correlation function, and the precision of an extracted result is remarkably improved. Determinant logarithms of symmetrical positive definite matrixes in the joint likelihood function are calculated by utilizing an LU (Logic Unit), and the problem of unstable number value occurring in direct calculation is solved.

Description

technical field [0001] The invention belongs to the field of integrated circuits, and in particular relates to a method for establishing a spatial correlation model of process deviation in an integrated circuit chip. Background technique [0002] With the rapid development of integrated circuit manufacturing technology, the feature size of integrated circuit chips is continuously reduced. Today, the characteristic size of integrated circuit MOS tubes has reached the nanometer level, and the semiconductor manufacturing industry has entered the era of nanotechnology. Under the complex nano-manufacturing process, the geometric and electrical parameter characteristic values ​​of integrated circuit devices and interconnection lines (such as the effective channel length of MOS transistors, interconnection line width and height, threshold voltage, etc.) Simple, definite design nominal values, but some form of probability density distribution around the nominal values. This proces...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F17/50
Inventor 曾璇陆伟成陶俊严昌浩付强
Owner FUDAN UNIV
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