Manufacturing method of power semiconductor device

Abstract

The invention is suitable for the technical field of semiconductors and provides a power semiconductor device and a manufacturing method thereof. The power semiconductor device comprises a semiconductor layer formed on a semiconductor substrate and a well region formed on the semiconductor layer, wherein the middle of the well region is filled with an electrode contact layer which is flush with the surface of the semiconductor layer; both sides of the electrode contact layer are provided with transversely diffused source regions; the bottom surface of the electrode contact layer is provided with a diffusion deep well; and the source regions, the deep well region and the electrode contact layer are contacted pairwise. In the invention, the middle part of the well region formed on the semiconductor layer is hollowed and filled with the electrode contact layer which is flush with the surface of the semiconductor layer, the side faces of the electrode contact layer is provided with the transversely diffused source regions and the sizes of the source regions are fully defined by transverse diffusion widths, so that the transverse sizes of the source regions of the device can be minimized, a transverse resistance which is parasitic under a P-well middle source region is reduced, a parasitic NPN tube is prevented from working in the amplification state and the latch-up of the device is restrained.

Description

technical field [0001] The invention belongs to the technical field of semiconductors, and in particular relates to a manufacturing method of a power semiconductor device. Background technique [0002] It is well known that the latch-up effect is the main factor limiting the operating current of gated transistors in power semiconductor devices. If the hole flow of the p-well channel formed under the n+ source region increases, a voltage difference exists between the p-well and the source region. When the voltage difference is higher than a certain value (about 0.7V), that is, the emitter and base of the parasitic NPN transistor are generally forward-biased, the parasitic transistor in the gate-controlled transistor starts to work, and the device latches up. Latch-up not only causes the gate of the device to lose its control function, but in severe cases, the current of the device continues to increase, causing the temperature of the chip to rise until it burns out. [000...

AI Technical Summary

Problems solved by technology

This method requires the development of a process for injecting metal (Ti, Co, Mo) ions with high energy, and the buried electrode formed by this method is not a real metal or conductor electrode, but a semiconductor doped with metal ions. Whether the effect is Better than a semiconductor doped with a high concentration of P-type materials remains to be verified

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