Method for improving aligning performance in polysilicon grid making technology

Abstract

A method for improving aligning performance in polysilicon grid making technology comprises the steps of: providing a semiconductor substrate, wherein the semiconductor substrate has a zero-aligning mark, a gate oxide layer and a polysilicon layer used for making polysilicon grid; forming a mask pattern on the polysilicon layer, wherein an opening of the mask pattern is correspond to the zero-aligning mark; etching the polysilicon layer, the gate oxide layer to the zero-aligning mark successively; removing the mask pattern; and aligning the zero-aligning mark on the semiconductor substrate with an aligning mark on the mask board. The method avoids the imperfect alignment phenomenon caused by unclear zero-aligning mark, and improves the accuracy of alignment.

Description

technical field [0001] The invention relates to the field of semiconductor devices and fabrication, in particular to a method for improving alignment performance in a fabrication process of polysilicon gates. Background technique [0002] With the development of semiconductor technology, the area of ​​semiconductor chips is getting smaller and smaller, and the line width in the chip is also shrinking. Therefore, the test of semiconductor process capability is also increasing, and the control of process accuracy and process variation has also become more and more important. more important. In the process of manufacturing semiconductor chips, the most important process is lithography, which is a process of transferring the mask pattern to the wafer through a series of steps such as alignment, exposure, and etching. Therefore, lithography The quality of the process will directly affect the performance of the final chip. [0003] In the lithography process, in order to correct...

AI Technical Summary

Problems solved by technology

[0005] For Electrically Erasable Programmable ReadOnly Memory (EEPROM), during the fabrication of polysilicon gates, it often happens that the zero alignment mark on the wafer cannot be identified, resulting in the wafer being returned, or The zero alignment mark is relatively vague. Although it has not been returned, it is difficult to completely align with the zero alignment mark on the mask during the manufacturing process, resulting in a decrease in alignment accuracy.

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