Method for improving etching selection ratio of etched hard mask oxidation layer to etched silicon nitride layer

Abstract

The invention discloses a method for improving the etching selection ratio of an etched hard mask oxidation layer to an etched silicon nitride layer. The hard mask oxidation layer is etched in an etching reaction cavity; and when the hard mask oxidation layer is etched, fluorine-containing etching gas and oxygen in a ratio of 0.25-2 are introduced into the etching reaction cavity, and the source power in the etching reaction cavity is 0 to 100 watts. The method can greatly improve the etching selection ratio of the hard mask oxidation layer to the silicon nitride layer.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a method for improving the etching selectivity ratio of etching a hard mask oxide layer and a silicon nitride layer. Background technique [0002] Currently, in the manufacture of semiconductor devices, silicon nitride can be used to induce stress in the transistor channel, thereby adjusting the carrier mobility in the channel. Complementary Metal-Oxide-Semiconductor (CMOS) structures include NMOS structures and PMOS structures. For CMOS structures, it is necessary to deposit a silicon nitride layer with tensile stress (tensile stress) on the NMOS structures. A silicon nitride layer with compressive stress is deposited on the structure to ensure that the carriers in the channels of the NMOS structure and the PMOS structure have the same mobility. [0003] The manufacturing method of the CMOS structure in the prior art, combined with its specific cross-section...

AI Technical Summary

Problems solved by technology

So in such as Figure 1c In the figure shown, when the exposed HMO 107 is etched using the patterned photoresist layer 108 as a mask, it is first necessary to ensure that the HMO 107 and the underlying silicon nitride layer 106 with tensile stress have a very high Etching selectivity, not only remove the hard mask oxide layer on other positions, but also remove all the thicker hard mask oxide layer on the area between the gate and the gate, otherwise, if the gate and the gate If there is still a hard mask oxide layer in the area between the hard mask oxide layer, the silicon nitride layer 106 with tensile stress under the hard mask oxide layer cannot be removed in the subsequent process, which seriously affects the progress of the process.

[0016] Moreover, if the HMO107 and the underlying silicon nitride layer 106 with tensile stress have a very high etching selectivity ratio, when the exposed HMO107 is etched using the patterned photoresist layer 108 as a mask, The hard mask oxide etch at the sharp corners of the polysilicon gate is faster than other positions, such as Figure 1b As shown by the dotted circle in , in order to ensure that the thicker HMO 107 on the area between the gate and the gate is completely removed, it is easy to etch the silicon nitride layer 106 with tensile stress below it, and it will be etched when it is severe to the polysilicon gate, causing damage to the semiconductor device

Images