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Overcurrent protection circuit

A technology of overcurrent protection circuit and unit circuit, which is applied in the direction of emergency protection circuit device, emergency protection circuit device for limiting overcurrent/overvoltage, circuit device, etc. Low-level problems, to achieve the effect of reducing shutdown power consumption, improving reliability, and ensuring accurate sampling

Active Publication Date: 2014-04-23
ARKMICRO TECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] The technical problem to be solved by the present invention is to solve the problem of low reliability of the over-current protection circuit in the prior art and large power consumption during over-current shutdown. To solve this technical problem, the present invention proposes a The overcurrent protection circuit of the device, the circuit includes the amplifier AMP1, the amplifier AMP2, the pull-up tube M1, the sampling tube M2, the power tube M p , NMOS tube M8, resistor R1, resistor R2 and resistor R s ; Among them, the pull-up tube M1, the sampling tube M2, the power tube M p All are PMOS tubes; sampling tube M2, NMOS tube M8 and resistor R s Connected in series between the power supply and the ground, the power tube M p , resistor R1, and resistor R2 are sequentially connected in series between the power supply and the ground; the sampling tube M2 and the power tube M p Mirror connection; the positive terminal of the amplifier AMP2 is connected to the drain of the sampling tube M2, and the negative terminal is connected to the power tube M p Between the drain resistor R1, the output terminal of the amplifier AMP2 is connected to the gate of the NMOS transistor M8, and the source of the NMOS transistor M8 is connected to the negative terminal of the amplifier AMP1, and the positive terminal of the amplifier AMP1 is connected to the reference voltage V ref , The output terminal is connected to the gate of the pull-up tube M1, and the source and drain of the pull-up tube M1 are respectively connected to the power supply and the mirror-connected sampling tube M2 and power tube M p the grid

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Embodiment approach 1

[0017] Such as figure 2 Shown is a circuit structure diagram of a specific embodiment of the present invention, the circuit structure includes amplifier AMP1, amplifier AMP2, pull-up tube M1, sampling tube M2, NMOS tube M8 and resistor R s ; Among them, the sampling tube M2, the NMOS tube M8 and the resistor R s Connected in series between power supply and ground, and power tube M p The branches are connected in parallel; sampling tube M2 and power tube M p Mirror connection, the positive terminal and negative terminal of the amplifier AMP2 are respectively connected to the sampling tube M2 and the power tube M p The drain of the amplifier AMP2 is connected to the gate of the NMOS transistor M8, and the source of the NMOS transistor M8 is connected to the negative terminal of the amplifier AMP1, and the positive terminal of the amplifier AMP1 is connected to the reference voltage V ref , The output terminal is connected to the gate of the pull-up transistor M1, and the sou...

Embodiment approach 2

[0024] In order to reduce the turn-off power consumption of the circuit, this specific embodiment adds a unit circuit for reducing the turn-off power consumption on the basis of the first embodiment, the unit circuit includes PMOS transistors M3, M4, M5, NMOS transistors M6 and M7, Resistors R3 and R4, wherein the PMOS transistor M4, PMOS transistor M5, NMOS transistor M6 and resistor R4 are connected in series between the power supply and the ground, and the gate and drain of the NMOS transistor M6 are connected; the PMOS transistor M3 is connected to the gate of the PMOS transistor M4 and Between the power supply, and the gate of the PMOS transistor M3 is connected to the power supply through the resistor R3; the NMOS transistor M7 is connected between the gate of the PMOS transistor M3 and the gate of the PMOS transistor M5, and the gate is connected to the gate of the NMOS transistor M6 ; In addition, the gate of the PMOS tube M4 is the port one of the unit circuit for redu...

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Abstract

The invention discloses an overcurrent protection circuit used for a voltage stabilizer. The circuit comprises an amplifier AMP1, an amplifier AMP2, a pull-up tube M1, a sampling tube M2, an N-channel metal oxide semiconductor (NMOS) transistor M8 and a resistor Rs; simultaneously, the overcurrent protection circuit also comprises a unit circuit which reduces shutdown power consumption, wherein the first port of the unit circuit which reduces the shutdown power consumption is connected with the grid of a power tube Mp; and the second port is connected with the drain of the power tube. The overcurrent protection circuit can accurately sample an output current and provide reliable overcurrent protection for the circuit, has low overcurrent shutdown power consumption of a system, and reduces unnecessary power consumption.

Description

technical field [0001] The invention relates to an analog integrated circuit, in particular to an analog integrated circuit which protects the circuit. Background technique [0002] Due to the continuous development of VLSI, the integration of power chips has developed rapidly and is widely used in various devices, especially in portable electronic products. [0003] Low-dropout linear regulator (LDO) is an important branch of power IC. Compared with DC / DC converter, it has the advantages of small ripple, low cost, small quiescent current and no inductor. It is the first choice for portable products. One of the power supply systems. [0004] For the power supply system, due to various improper use, the power supply system will be damaged, especially for the system on chip. The damage of the power supply will directly lead to the collapse of the entire chip. Therefore, in the protection function of the power supply, an overcurrent protection circuit is generally required to...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H02H9/02
Inventor 吴玉强刘敬波马芝胡江鸣周生明石岭
Owner ARKMICRO TECH