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Method for modeling P-channel metal oxide semiconductor (PMOS) one-time programmable memory (OTP) device

A modeling method and device technology, which can be used in instruments, special data processing applications, electrical digital data processing, etc., and can solve problems such as small area and short writing time.

Active Publication Date: 2011-06-01
SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The PMOS OTP device has the advantages of small area and short writing time, but its device characteristics are very different from those of conventional field effect transistors. The SPICE model of ordinary field effect transistors can no longer be used to describe this device, so it is necessary to develop A new type of equivalent circuit model to describe it

Method used

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  • Method for modeling P-channel metal oxide semiconductor (PMOS) one-time programmable memory (OTP) device
  • Method for modeling P-channel metal oxide semiconductor (PMOS) one-time programmable memory (OTP) device
  • Method for modeling P-channel metal oxide semiconductor (PMOS) one-time programmable memory (OTP) device

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Embodiment Construction

[0016] like image 3 Shown is the flowchart of the modeling method of PMOS OTP device of the present invention, and the present invention comprises the steps:

[0017] Step 1. Establish a set of equivalent circuits according to the structure and working principle of the PMOS OTP device. like Figure 4 As shown, the equivalent circuit structure includes: a PMOS selection transistor, a PMOS floating gate transistor, the PMOS selection transistor and the PMOS floating gate transistor form a series structure in which the drain end of the PMOS selection transistor is connected to the source end of the PMOS floating gate transistor The body potential of the PMOS selection transistor and the PMOS floating gate transistor is connected in series, the source terminal of the PMOS selection transistor is connected to the source voltage, and the gate is connected to the gate voltage; the drain terminal of the PMOS floating gate transistor is connected to the drain voltage, and the drain t...

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Abstract

The invention discloses a method for modeling a P-channel metal oxide semiconductor (PMOS) one-time programmable memory (OTP) device. In the method, an equivalent circuit is established according to the structure and working principle of the PMOS OTP device; the structure of the equivalent circuit mainly comprises a PMOS selection transistor and a PMOS floating gate transistor, wherein the selection transistor and the floating gate transistor form a serial connection structure, and have the same bulk potential; a parasitic diode is connected between the drain terminal and bulk potential of the floating gate transistor; the gate of the floating gate transistor is connected with a voltage controlled voltage source for simulating the gate coupling voltage of the floating gate transistor; the voltage of the voltage controlled voltage source is proportional to the gate source voltage difference of the selection transistor, and the proportional coefficient is fixed; and a corresponding simulation program with integrated circuit emphasis (SPICE) macro-model is established according to the equivalent circuit. The method has physical significance while being used for well describing the electric characteristic of the PMOS OTP device.

Description

technical field [0001] The invention relates to the field of semiconductor integrated circuits, in particular to a modeling method for a PMOS OTP device Background technique [0002] The PMOS OTP (one-time programmable memory) device is a new type of storage device that realizes electronic writing by dividing the voltage of the coupling capacitance of the field effect transistor. Its device structure is as figure 1 As shown, it is a series connection of two P-type MOS field effect transistors (PMOS). The two PMOS devices are made in the same N well. The left PMOS is a PMOS selection transistor, and the gate of the PMOS selection transistor is used as a gate voltage input terminal. The gate of the PMOS selection transistor is a polysilicon gate; the PMOS on the right is a PMOS floating gate transistor, and the gate of the PMOS floating gate transistor is a floating gate, and the floating gate is used to store charges. The grid is not connected to any potential. The drain e...

Claims

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Application Information

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IPC IPC(8): G06F17/50H01L27/088
Inventor 王正楠
Owner SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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