Method for enhancing welding reliability of high-frequency quad flat no lead (QFN) device

A reliability and device technology, which is applied in the field of reliable welding of high-frequency QFN devices, can solve problems such as QFN device failure, increased solder joint stress, and increased assembly stress, so as to solve the problem of increased welding stress, reduced thermal stress, and reduced The effect of welding stress

Active Publication Date: 2011-06-01
BEIJING RES INST OF TELEMETRY
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

This assembly mode ensures a good grounding effect, but it will increase the stress of the solder joints. The main reason is: first, the device needs to be soldered to the printed board with high-temperature solder, and then soldered into the shell along with the printed board. The device has undergone two welding processes, resulting in a large welding stress; secondly, when the printed board is soldered and cooled, the shrinkage stress of the solder is transmitted to the device through the printed boar

Method used

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  • Method for enhancing welding reliability of high-frequency quad flat no lead (QFN) device
  • Method for enhancing welding reliability of high-frequency quad flat no lead (QFN) device
  • Method for enhancing welding reliability of high-frequency quad flat no lead (QFN) device

Examples

Experimental program
Comparison scheme
Effect test

Example Embodiment

[0031] Example 1:

[0032] The assembling method designed by the invention is adopted, that is, a lining board is added between the printed board and the shell, the lining board material is brass H62 (thermal expansion coefficient 16ppm / ℃), and the thickness is 2mm. The number of test pieces is 4 pieces, numbered B01~B04.

[0033] 1. Basic conditions

[0034] (1) Printed board

[0035] In order to effectively verify the welding quality of QFN devices, the printed circuit board in this embodiment is simplified to avoid introducing other factors, such as Figure 4 Shown is a schematic diagram of the structure of the printed board of the present invention. In the figure, the surrounding pin pads and belly ground pads of the printed board corresponding to the QFN device can be clearly seen. The printed board is made of Rogers 4350B and has a thickness of 0.254 mm.

[0036] (2) Components

[0037] According to the printed circuit board design, see Table 1 for the supporting components of a ...

Example Embodiment

[0075] Example 2:

[0076] The assembly method designed in the present invention is adopted, namely: a liner is added between the printed board and the shell, and the material of the liner is Kefa alloy (thermal expansion coefficient 8ppm / °C). The number of test pieces is 4 pieces, numbered C01~C04.

[0077] 1. Basic conditions

[0078] (1) Printed board

[0079] Same as "Example" 1.

[0080] (2) Components

[0081] Same as "Example 1".

[0082] (3) Solder and flux

[0083] Same as "Example 1".

[0084] (4) Production and testing tools and equipment

[0085] Same as "Example 1".

[0086] 2. Process implementation steps

[0087] Step (1), component matching

[0088] Same as "Example 1".

[0089] Step (2),

[0090] Same as "Example 1".

[0091] Step (3),

[0092] Same as "Example 1".

[0093] Step (4),

[0094] Same as "Example 1".

[0095] Step (5), solder paste is missing

[0096] Same as "Example 1".

[0097] Step (6) Patch

[0098] Same as "Example 1".

[0099] Step (7), reflow soldering

[0100] Same a...

Example Embodiment

[0107] Example 3:

[0108] The assembly method designed in the present invention is adopted, namely: a liner is added between the printed board and the shell, and the material of the liner is Kefa alloy (thermal expansion coefficient 8ppm / °C). The amount of solder paste applied to the solder joints of the device is controlled by adjusting the size of the leakage plate opening. A 0.15mm thick leakage plate is selected. The size of the leakage plate opening is appropriately reduced relative to the size of the pad. The shrinkage ratio is: 70% of the surrounding pin pads 4. 4 test pieces with 65% of the belly ground pads, numbered D01~D04; 4 pieces of test pieces with 56% of the surrounding pin pads and 51% of the belly ground pads, numbered D05~D08.

[0109] 1. Basic conditions

[0110] (1) Printed board

[0111] Same as "Example 1".

[0112] (2) Components

[0113] Same as "Example 1".

[0114] (3) Solder and flux

[0115] Same as "Example 1".

[0116] (4) Production and testing tools and e...

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Abstract

The invention relates to a method for enhancing the welding reliability of a high-frequency quad flat no lead (QFN) device. The method comprises the following steps of: (1) uniformly coating a high-temperature solder with the smelting point of between 214 and 220 DEG C on a lining board and welding a printed board on the lining board; (2) coating a low-temperature solder with the smelting point of between 180 and 188 DEG C on a bonding pad of the printed board by using a bushing, sticking the QFN device and welding, wherein the opening size of the bushing is smaller than that of the bonding pad of the printed board; and (3) fastening the lining board in a shell. Through a welding method, secondary heating of the device is avoided, welding stress is reduced and good mechanical support is provided for the printed board assembly on the basis of ensuring that a printed board assembly is fully grounded; simultaneously, thermal stress produced by a component under a cold and heat exchange condition can be greatly reduced and the reliability of the QFN device is enhanced.

Description

technical field [0001] The invention belongs to the technical field of electronic assembly, and in particular relates to a process method for realizing reliable welding of high-frequency QFN devices. Background technique [0002] Quad Flat No Lead (hereinafter referred to as QFN) is a relatively new form of IC packaging. The appearance of QFN devices is square or rectangular, the size is close to CSP, and it is very thin and light. The bottom of the component has a solder end that is horizontal to the bottom surface. There is a large-area exposed solder end in the center for heat conduction. There are I / O solder terminals for electrical connection around the periphery of the large solder end. QFN uses peripheral pins to make PCB wiring more efficient. Flexible, central exposed braze termination provides good thermal and electrical performance. These characteristics make QFN widely used in some electronic products with high volume, weight, thermal performance and high freque...

Claims

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Application Information

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IPC IPC(8): H05K3/34
Inventor 何伟孙奕庭齐凤海
Owner BEIJING RES INST OF TELEMETRY
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