Switch-body PMOS switch with switch-body dummies

Abstract

The present invention provides a switch-body PMOS switch with switch-body dummies, concretely a sample-and-hold feed switch having parallel branches, each extending from an input node to an output node connected to a hold capacitor. Each branch has a PMOS switch FET connected to a matching PMOS dummy FET. A sample clock switches the PMOS switch FETs on and off, and a synchronous inverse sample clock effects complementary on-off switching of the PMOS dummy FETs. Concurrently, a synchronous inverse sample clock switches the NMOS switch FETs on and off, and the sample clock effects a complementary on-off switching of the NMOS dummy FETs. A bias sequencer circuit biases the bodies of the PMOS switch FETs and the bodies of the PMOS dummy FETs, in a complementary manner, and biases the NMOS switch FETs and the NMOS dummy FETs, also in a complementary manner. The on-off switching of the PMOS dummy FETs injects charge, cancelling a charge injection by the PMOS signal switch FETs, and injects glitches cancelling glitches injected by the PMOS signal switch FETs. The on-off switching of the NMOS dummy FETs injects charge that cancels a charge injection by the NMOS signal switch FETs, and injects glitches that cancels glitches injected by the NMOS signal switch FETs.

Description

Technical field [0001] The present invention generally relates to circuits for sampling and holding instantaneous values ​​of time-varying electrical signals. Background technique [0002] The sample and hold circuit receives an electrical signal having one or more time-varying properties (for example, amplitude or phase), and acquires and holds samples of the signal in response to a sampling command event (for example, clock edge). [0003] Sample and hold devices (hereinafter generally referred to as "S / H devices") are used in many applications, for example, pre-samplers in or before the front end of an analog-to-digital converter ("ADC"), typically used Provide a value to the ADC's comparator, which is moderately stable for a long enough time to meet the ADC setup and hold time requirements; or a "de-aliasing device" installed at the output of the digital-to-analog converter ("DAC") ( de-glitcher), typically used to sample the DAC output at some point after the DAC clock, and t...

AI Technical Summary

Problems solved by technology

An inherent problem with single-transistor PMOS FET or NMOS FET structures is that they require a threshold gate-source voltage (commonly referred to as V TH ) to turn on, meaning that a conductive channel is formed extending from source to drain under the gate

Although these and other methods have been known for a long time, acceptable S / H device performance has not been achieved in many applications

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