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Digital downconverter with variable bandwidth and implementation method thereof

A digital down-converter and variable bandwidth technology, applied in the electronic field, can solve the problems of multiplier operating frequency reduction, fixed processing bandwidth, unsuitable for wideband digital receivers, etc., and achieve the effect of flexible configuration, high-efficiency and high-speed processing

Inactive Publication Date: 2011-06-15
UNIV OF ELECTRONICS SCI & TECH OF CHINA
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

In the prior art, ASIC (Application Specific Integrated Circuit) single-channel digital downconverter is generally used. Although the processing bandwidth can be variable, the maximum input data sampling rate generally does not exceed 100MHz, and because it uses multi-level The traditional down-conversion structure of cascaded integral comb filter CIC (Cascade Integrator Comb Filter), so the processing bandwidth is narrow, generally no more than 1MHz, not suitable as a digital down-converter for wideband digital receivers
The broadband DDC (Digital Down-Converter) based on the polyphase filter structure can process broadband signals, but the processing bandwidth is fixed, and when the bandwidth of the signal to be processed is very narrow, because the decimation factor becomes larger, the number of multipliers required increases, but the multiplication The operating frequency of the server is reduced, so its resource utilization is very low

Method used

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  • Digital downconverter with variable bandwidth and implementation method thereof
  • Digital downconverter with variable bandwidth and implementation method thereof
  • Digital downconverter with variable bandwidth and implementation method thereof

Examples

Experimental program
Comparison scheme
Effect test

specific Embodiment 1

[0054] Set the system parameters as follows:

[0055] (1) Realize digital down-conversion, reduce the signal data rate, reduce the AD sampling rate of 100MSPS by 131072 times, and output the baseband signal data rate of 762.94SPS.

[0056] (2) The carrier frequency of the intermediate frequency signal is 32.4MHz, and the signal bandwidth is 150Hz.

[0057] (3) Complete output signal shaping to meet subsequent signal processing requirements.

[0058] Receive external signals to set the parameter configuration module, the required parameters are as follows:

[0059] (1) The width of the NCO phase accumulation word (phi_inc_i) is 27 bits, and the frequency of the NCO output local oscillator signal can be changed by changing the value of the phase accumulation , whose calculation formula is: . When the NCO output local oscillator frequency is 32.4MHz, . NCO is implemented using the CORDIC algorithm, and the structure is as follows Image 6 As shown, a 16-stage pipeline i...

specific Embodiment 2

[0067] Set the system parameters as follows:

[0068] (1) Realize digital down-conversion, reduce the signal data rate, reduce the AD sampling rate 100MSPS by 2 times, and output the baseband signal data rate 50MSPS.

[0069] (2) The carrier frequency of the intermediate frequency signal is 21.4MHz, and the signal bandwidth is 40MHz.

[0070] (3) Complete output signal shaping to meet subsequent signal processing requirements.

[0071] Receive external signals to set the parameter configuration module, the required parameters are as follows:

[0072] (1) The width of the NCO phase accumulation word (phi_inc_i) is 27 bits, and the frequency of the NCO output local oscillator signal can be changed by changing the value of the phase accumulation , whose calculation formula is: . When the NCO output local oscillator frequency is 21.4MHz, . NCO is realized by CORDIC algorithm, the structure is as follows Figure 4 As shown, a 16-stage pipeline is adopted.

[0073] (2) Co...

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PUM

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Abstract

The invention belongs to the field of electronics, and discloses a digital downconverter with variable bandwidth. The digital downconverter comprises a path switching circuit, a narrow-band filter group and a wide-band filter, wherein the path switching circuit is used for selecting a proper processing path for signals in accordance with configuration of parameter configuration modules; the narrow-band filter group is used for processing input narrow-band signals based on the structure of the digital downconverter; and the wide-band filter is used for processing input wide-band signals or the output of the narrow-band filter group based on a multiphase filter structure. The invention also provides an implementation method of the digital downconverter with variable bandwidth. The digital downconverter with variable bandwidth integrates the advantages of a traditional digital downconverter structure with a single channel and the advantages of the multiphase filter structure into a whole, thus implementing high efficient and high-speed processing on input intermediate-frequency signals, and being capable of flexibly configuring signal processing bandwidth within a larger range.

Description

technical field [0001] The invention relates to the field of electronics, in particular to a variable-bandwidth digital down-converter for signals and a realization method. Background technique [0002] Variable Bandwidth Digital Down-Converter (VB-DDC) can process input signals of various bandwidths, so it is widely used in radar, communication, electronic reconnaissance, etc. In the prior art, ASIC (Application Specific Integrated Circuit) single-channel digital downconverter is generally used. Although the processing bandwidth can be variable, the maximum input data sampling rate generally does not exceed 100MHz, and because it uses multi-level Cascade Integrator Comb Filter CIC (Cascade Integrator Comb Filter) is a traditional down-conversion structure, so the processing bandwidth is narrow, generally no more than 1MHz, and it is not suitable as a digital down-converter for wideband digital receivers. The broadband DDC (Digital Down-Converter) based on the polyphase fil...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03D7/16
Inventor 夏威王晓何子述
Owner UNIV OF ELECTRONICS SCI & TECH OF CHINA
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