Method for carrying out optimized speed classification for digital integrated circuit with transparent latch

Abstract

The invention relates to a method for carrying out optimized speed classification for a digital integrated circuit with a transparent latch under the effect of process deviation, which belongs to the field of integrated circuits and comprises the following steps; computing the minimum clock cycle accumulative density distribution function of the digital integrated circuit with the transparent latch and determining an optimal clock cycle classification demarcation point and an optimal test sequence of the demarcation point according to the minimum clock cycle accumulative density distribution function to maximize the total income. The method can obtain the work clock cycle distribution of the transparent latch circuit through a random configuration method based on very low computation complexity and very high solution accuracy to avoid the convergence problem in a random arrival time solution; the optimal test sequence of the cycle classification demarcation point can be determined through an optimization method of which computation complexity only is 0 (n log n) so as to minimize the test cost; and when the position of the cycle classification demarcation point is determined by a greedy algorithm to maximize the circuit design income, the optimality of each iterative computation can be ensured in theory.

Description

technical field [0001] The invention belongs to the field of integrated circuits, and in particular relates to a method for optimizing speed classification for digital integrated circuits with transparent latches under the influence of process deviations. Background technique [0002] As the integrated circuit technology enters the nanometer level, the process deviation in circuit manufacturing is becoming more and more serious, which brings serious circuit performance uncertainty and circuit operating frequency dispersion. In order to improve the revenue of circuit manufacturing, B.D.Cory, R.Kapur and B.Underwood proposed the concept of speed binning in 2003 (B.D.Cory, R.Kapur, and B.Underwood, "Speed ​​Binning with Path Delay Test in 150-nm Technology”, IEEE Design Test Comput., 20(5), pp.41-45, 2003.), all the output circuits can be sorted according to the minimum clock cycle that can work normally, and the cycle level is divided, and then Create different sell prices fo...

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Problems solved by technology

However, it is difficult for this type of method to obtain a random clock cycle distribution that includes all clock frequency points, unless this type of SSTA method is used at every possible clock cycle point to obtain the yield there, which is very time-consuming

In addition, because in the iterative process, the time series random variable needs to be updated according to the results of the previous iterations, and there is a statistical correlation between the variable itself and the variable of this iteration, which will lead to problems in this type of algorithm. The phenomenon of statistical autocorrelation finally leads more or less to the non-convergence problem of the random arrival times of these algorithms

In addition, the existing methods usually assume that the process deviation has the characteristics of Gaussian distribution, but this assumption is not necessarily satisfied in the actual IC production

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