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Method of forming shallow trench isolation structure

An isolation structure and shallow trench technology, applied in electrical components, semiconductor/solid-state device manufacturing, circuits, etc., can solve problems such as reducing the qualification rate of components and affecting electrical performance, and achieve the effect of improving breakdown voltage

Active Publication Date: 2011-08-17
TAIWAN SEMICON MFG CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

For example, N-well P + The breakdown voltage between the adjacent P well is about 7V, and many shallow trench isolation (STI) fabricated by traditional methods cannot meet this goal
The electrical performance of a shallow trench isolation (STI) component with poor isolation effect will be affected, and the component yield will be reduced

Method used

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  • Method of forming shallow trench isolation structure
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  • Method of forming shallow trench isolation structure

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Embodiment Construction

[0029] The methods of making and using the embodiments of the present invention will be discussed in detail below. The disclosure of the invention provides many possible inventive steps which can be presented in broad language; however, the specific embodiments discussed are intended only to illustrate specific ways to make and use the invention, and do not limit the scope of the invention.

[0030] Figure 1-3B A first embodiment of the present invention is disclosed. Please refer to figure 1 , which shows a substrate 101 covered by a mask layer 102 , wherein the mask layer 102 exposes a trench 103 separating the active regions 105 of the top surface 104 of the substrate 101 . Substrate 101 may include bulk doped or undoped silicon, or an active layer of a silicon-on-insulator (SOI) substrate. Generally, a silicon-on-insulator (SOI) substrate includes an active layer of a semiconductor material such as silicon, germanium, silicon germanium, silicon germanium on insulator ...

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PUM

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Abstract

An embodiment of the disclosure includes a method of forming a shallow trench isolation structure. A substrate is provided. The substrate includes a top surface. A trench is formed extending from the top surface into the substrate. The trench has sidewalls and a bottom surface. A liner oxide layer is formed on the sidewalls and the bottom surface. The liner oxide layer is treated in a plasma environment comprises at least one of NF3, F2, and BF2. The trench is filled with a dielectric layer. The method provided in the invention can improve the breakdown voltages of the elements on the substrate.

Description

technical field [0001] The invention relates to a system and method for manufacturing semiconductor elements, in particular to a method for manufacturing shallow trench isolation structures. Background technique [0002] Generally speaking, shallow trench isolation (STI) is used to separate and isolate active regions on a semiconductor wafer, so as to isolate the active regions from each other. Methods of forming shallow trench isolation (STI) include etching the trenches, filling the trenches with a dielectric material such as oxide, and removing any excess oxide with a chemical mechanical polishing (CMP) process or etching process to remove Dielectric material outside the trench. The dielectric material is used to electrically isolate the active regions from each other. [0003] Shallow trench isolation (STI) fabricated by conventional methods may not provide sufficient isolation. For some products, especially high-voltage components, the shallow trench isolation breakd...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/762
CPCH01L21/76224
Inventor 陈能国曾国华蔡正原
Owner TAIWAN SEMICON MFG CO LTD