Terminal structure of power semiconductor device and power semiconductor device

Abstract

The invention provides a terminal structure of a power semiconductor device and a power semiconductor device. The terminal structure of the power semiconductor device comprises a channel ring in the main body semiconductor area of the power semiconductor device, wherein the material of the channel ring is intrinsic polycrystalline material whose relative dielectric constant is a value from 1 to 15, and the intrinsic polycrystalline material is intrinsic polycrystalline silicon carbide. In the invention, the intrinsic polycrystalline silicon carbide with relative dielectric constant within15 is used in the channel ring in the terminal structure of the power semiconductor device. Thus electric field line which goes through the channel ring area is nearly level. There is no extreme point in the area. The carrier hold-up is substantially reduced. Thereby breakdown voltage is raised.

Description

Technical field [0001] The invention belongs to the technical field of semiconductor device protection, and in particular relates to a terminal structure of a power semiconductor device and a power semiconductor device. Background technique [0002] The electric field confinement ring, referred to as the field ring, is one of the commonly used terminals of power semiconductor devices. The application of the field ring can improve the fringe electric field distribution of the power semiconductor device, and improve the voltage resistance and stability of the power semiconductor device. figure 1 It is a schematic diagram of the terminal structure of an existing power semiconductor device. Please refer to figure 1 , The power semiconductor device includes a heavily doped N-type substrate 1 (N+ substrate 1), an N-type buffer layer 2 on the N+ substrate 1, a lightly doped N-type epitaxial layer 3 on the N-type buffer layer 2 (N-type epitaxial layer 3) and functional regions and prote...

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Problems solved by technology

from Figure 2B We can get that the electric field curve of the depletion layer has multiple peaks and troughs, so its withstand voltage does not reach the maximum, which limits the axial withstand voltage capability of the power semiconductor

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