3D-RESURF junction terminal structure of power semiconductor
A technology for power semiconductors and junction terminals, applied in semiconductor devices, electrical components, circuits, etc., can solve problems such as unfavorable mass production, difficulty in obtaining repeatability, and drop in breakdown voltage, increasing the difficulty of the manufacturing process and reducing the disadvantages. Affect and reduce the effect of forward conduction loss
Inactive Publication Date: 2014-01-15
UNIV OF ELECTRONICS SCI & TECH OF CHINA +1
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Problems solved by technology
These two junction termination technologies have high requirements for surface passivation and interface charge prevention technology, otherwise it will cause a drop in breakdown voltage, it is difficult to obtain good repeatability, and it is not conducive to mass production
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[0020] A 3D-RESURF junction termination structure for a power semiconductor device, such as image 3 As shown, it includes a heavily doped layer 15, a metallized anode 14 located on the back of the heavily doped layer 15, and a N - Layer 16, N - P-type heavily doped regions 12 and N connected to the active region of the power semiconductor device at the top of layer 16 - The top of the layer 16 is away from the N-type heavily doped electric field stop ring 17 of the active region of the power semiconductor device, the metallized cathode 13 on the surface of the P-type heavily doped region 12, and the N-type metallized cathode 14 covering the metallized cathode 14. - The passivation layer 18 on the surface of the layer 16; it is characterized in that the N between the P-type heavily doped region 12 and the N-type heavily doped electric field stop ring 17 - The top of layer 16 has a P-type doped layer 19; the N between the P-type heavily doped region 12 and the N-type heavily d...
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The invention provides a 3D-RESURF junction terminal structure of a power semiconductor, belonging to the technical field of power semiconductor devices. In the structure, a P-type doping layer (19) is arranged on the top of a junction terminal power semiconductor pressurization region, namely, an N layer (16) between a P-type heavily doped region (12) connected with an active region of a device and an N-type heavily doped electric field cutting-off loop (17) of a far end of a junction terminal and a plurality of P-type doped rings (21) are arranged inside the structure; N-type doped regions (20) are distributed in the P-type doping layer (19) uniformly; and medium grooves are arranged in the P-type doping layer (19) and extend to the inside of a P-type doped loop (21) in the junction terminal structure. The junction terminal structure can be used to strengthen the pressurization of unit length of a device junction terminal, shorten terminal area and reduce forward conduction losses of a device. The surface is beneficial to decreasing negative influences of interfacial charges on breakdown voltage of the terminal relative to higher dosage concentration in a drift region and a capacity of the terminal to resist interfacial charges in a passivation layer can be strengthened.
Description
technical field [0001] The invention belongs to the technical field of power semiconductor devices and relates to a junction terminal structure of power semiconductor devices. Background technique [0002] Power electronics technology with power devices and power integrated circuits as the core and foundation is the key technology to achieve high efficiency and energy saving and promote mechatronics. It is a bridge between weak current control and strong current operation, and between information technology and advanced manufacturing technology. In the field of power electronics, power semiconductor devices are key components, and their characteristics play a vital role in the realization and improvement of system performance. One of the most notable features of power semiconductor devices is their high voltage blocking capability. However, for high-voltage power semiconductor devices, the edge breakdown caused by the edge curvature effect of the device has always been one ...
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IPC IPC(8): H01L29/06
Inventor 张金平李泽宏李巍张波
Owner UNIV OF ELECTRONICS SCI & TECH OF CHINA