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Method for fabricating self-aligned trench power semiconductor structure

A technology of power semiconductors and manufacturing methods, which is applied to semiconductor devices and other fields, and can solve problems such as critical voltage variation and avalanche resistance

Inactive Publication Date: 2011-11-30
KEXUAN MICROELECTRONICS
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Limited by the critical dimension of the trench and the contact window and the tolerance of alignment control, the distance between the gate trench 120 and the contact window 180 cannot be shortened arbitrarily, otherwise leakage current will easily occur, resulting in a critical voltage Mutation or avalanche resistance (UIS) ability decreased

Method used

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  • Method for fabricating self-aligned trench power semiconductor structure
  • Method for fabricating self-aligned trench power semiconductor structure
  • Method for fabricating self-aligned trench power semiconductor structure

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Embodiment Construction

[0060] The technical feature of the present invention utilizes the height difference between the hard mask and the polyetch back to form a spacer above the polysilicon gate. And using the space defined by the spacer layer structure, another step of polysilicon deposition and etch back (Poly deposition&etch back) is performed to form a polysilicon protruding structure. Since the thickness of the polysilicon protruding structure is relatively thin, the polysilicon protruding structure can be oxidized by a thermal oxidation process. The height difference between the silicon oxide protruding structure and the silicon substrate formed by the thermal oxidation process can be applied to fabricate the spacer structure to define the position of the contact window. In this way, the shortcoming of the traditional yellow light process that is prone to alignment errors can be avoided.

[0061] Figure 2A to Figure 2I It is the first embodiment of the manufacturing method of the trench ty...

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Abstract

The invention provides a method for manufacturing a self-aligned trench power semiconductor structure. The method comprises the following steps of: a) forming a trench polysilicon grid structure in a silicon base material; b) forming a self-aligned polysilicon extension structure which extends upwards from the trench polysilicon grid structure, wherein the self-aligned polysilicon extension structure is narrower than the trench polysilicon grid structure; c) oxidizing the self-aligned polysilicon extension structure to form a silicon oxide protrusion structure above the trench polysilicon grid structure; and d) forming a spacer structure on the side edge of the silicon oxide protrusion structure to define a source contact window in the silicon base material. In the manufacturing method provided by the invention, a spacing distance between the trench polysilicon grid structure and the source contact window is shortened by using a manufacture procedure of self-alignment, so that the limit of a lithography process can be overcome, yield control of the manufacture procedure can be enhanced, the characteristic uniformity of elements at different positions of a wafer can be improved, the cost is low and the feasibility is high.

Description

technical field [0001] The invention relates to a method for manufacturing a trench type power semiconductor structure, in particular to a method for manufacturing a self-aligned (self-aligned) trench type semiconductor structure. Background technique [0002] Figure 1A and Figure 1C It is a fabrication process of a typical trench power semiconductor structure. Such as Figure 1A As shown, firstly, a gate trench 120 is formed on a silicon substrate 110 . Subsequently, a gate oxide layer 130 is formed along the inner surface of the gate trench 120 . Next, deposit polysilicon material on the surface of the silicon substrate 110 , and remove excess polysilicon material by etching back to form a gate polysilicon structure 140 in the gate trench 120 . [0003] Next, if Figure 1B As shown, dopants are implanted into the silicon substrate 110 by ion implantation to form the body 150 surrounding the gate trench 120 . Then, dopants of different conductivity types are implante...

Claims

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Application Information

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IPC IPC(8): H01L21/28
Inventor 叶俊莹
Owner KEXUAN MICROELECTRONICS
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