Method for manufacturing multilayer stacked resistance switching memory
A technology of resistance conversion and manufacturing method, which is applied in the manufacture of semiconductor devices and the manufacture of resistance conversion memory, can solve problems such as incompatibility of resistance conversion memory technology, and achieve the effects of process compatibility, reduction of difficulty, and improvement of bonding strength
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Embodiment 1
[0032] Referring to FIG. 1, the present invention discloses a method for manufacturing a multilayer stacked resistance switching memory, which includes the following steps:
[0033] (A) first manufacture the first wafer, the first wafer includes peripheral circuits and at least one layer of resistance switching memory, and is planarized by chemical mechanical polishing. The chemical mechanical polishing used in the present invention can include two steps of rough polishing and fine polishing . The resistance switching memory includes a gate transistor array, a word / bit line, and a resistance switching memory cell array, and the first wafer may also include a multilayer resistance switching memory. Figure 1A In the figure, the peripheral circuit part is not drawn on the substrate 1, and the size of the figure is not drawn to scale, and there is a layer of resistance switching memory. In this example, the gate transistor used is a PN diode. Of course, other types of gate trans...
Embodiment 2
[0044] The difference between this embodiment and Embodiment 1 is that this embodiment is a method for manufacturing a bipolar transistor-gated three-dimensional stacked resistive switching memory.
[0045] It has also been described in the above-mentioned embodiments, and in Figure 1A and Figure 1B In the structure, a bipolar transistor can be used instead of the PN diode 4 as the gating transistor. If a bipolar transistor is used as the gating tube, Figure 1G The doped layers 10 and 14 formed in the above-mentioned method need to be changed into NPN layers or PNP layers accordingly, and the subsequent corresponding processes are similar to those in Embodiment 1, and will not be repeated here. finally got Figure 1M In the shown multi-layer stacked resistive memory structure, the difference is that the gating units used in the layers 24-26 are bipolar transistors.
Embodiment 3
[0047] (A) Figure 2A What is shown is the first wafer manufactured with peripheral circuits and a layer of resistive switching memory, and the peripheral circuits are also not shown, but it does not mean that the substrate 31 of the first wafer does not have peripheral circuits. The gating tube used in this case is a Schottky diode. Of course, other gating units can also be used, such as PN diodes and bipolar transistors. Here, the Schottky diode is used as an example, but it is not necessary to explain limited to Schottky diodes. Multiple Schottky diodes share one heavily doped semiconductor word line 32 , and the interface of the Schottky barrier formed by the Schottky diodes is the interface between the lightly doped semiconductor 34 and the electrode 35 . The electrode 35 is also the heating electrode of the storage unit 37, which can include a multilayer structure, for example, a metal that can form a Schottky contact with the lightly doped semiconductor 34 on the side ...
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