Method for manufacturing multilayer stacked resistance conversion memorizer
A technology of resistance conversion and manufacturing method, which is applied in semiconductor/solid-state device manufacturing, electric solid-state devices, circuits, etc., can solve the problems of resistance conversion memory technology incompatibility, etc., and achieve the effects of process compatibility, difficulty reduction, and bond strength improvement
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Embodiment 1
[0032] Referring to FIG. 1, the present invention discloses a method for manufacturing a multi-layer stacked resistance switching memory, which includes the following steps:
[0033] (A) First, a first wafer is manufactured. The first wafer includes peripheral circuits and at least one layer of resistance switching memory, and is planarized by chemical mechanical polishing. The chemical mechanical polishing used in the present invention can include two steps of rough polishing and fine polishing. . The resistance switching memory includes a strobe transistor array, word / bit lines and a resistance switching memory cell array, and the first wafer may further include a multi-layer resistance switching memory. Figure 1A The peripheral circuit portion is not drawn on the substrate 1, and the size shown in the figure is not drawn to scale, with a layer of resistance switching memory. In this example, the strobe used is a PN diode. Of course, other types of strobes can also be used...
Embodiment 2
[0044] The difference between this embodiment and the first embodiment is that this embodiment is a method for manufacturing a bipolar transistor gated three-dimensional stacked resistance switching memory.
[0045] It has also been explained in the above-mentioned embodiment, in Figure 1A and Figure 1B In the structure, a bipolar transistor can be used to replace the PN diode 4 as the strobe. If a bipolar transistor is used as the strobe, Figure 1G The doped layers 10 and 14 formed in the doped layers should be changed to NPN layers or PNP layers accordingly, and the subsequent corresponding processes are similar to those in the first embodiment, and will not be repeated here. finally got Figure 1M In the shown multi-layer stacked resistive memory structure, the difference is that the gate cells used in the layers 24-26 are bipolar transistors.
Embodiment 3
[0047] (A) Figure 2A Shown is a first wafer with peripheral circuits and a layer of resistance switching memory fabricated. Similarly, peripheral circuits are not shown, but this does not mean that the substrate 31 of the first wafer does not have peripheral circuits. The gate tube used in this case is a Schottky diode. Of course, other gate units can also be used, such as PN diodes and bipolar transistors. Here, a Schottky diode is used as an example, but it should be noted that it is not limited to Schottky diodes. A plurality of Schottky diodes share a heavily doped semiconductor word line 32 , and the interface of the Schottky barrier formed by the Schottky diodes is the interface between the lightly doped semiconductor 34 and the electrode 35 . The electrode 35 is also the heating electrode of the memory cell 37, which may comprise a multi-layer structure, for example, a metal that can form Schottky contact with the lightly doped semiconductor 34 on the side close to th...
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