In-situ melting and reflow process and system for forming flip-chip interconnects

Abstract

A method for fabricating a flip-chip semiconductor package comprising processing a semiconductor device, for example a semiconductor chip and processing a device carrier, for example a substrate. The semiconductor device comprises bump structures formed on a surface thereof. The substrate comprises bond pads formed on a surface thereof. The semiconductor chip is heated to a chip process temperature. The chip process temperature melts solder portions on the bump structures. The substrate is heated to a substrate process temperature, wherein said substrate process temperature may be different to the chip process temperature. The semiconductor chip is spatially aligned in relation to the substrate to correspondingly align the bump structures in relation to the bond pads. The semiconductor chip is displaced towards the substrate to abut the bump structures with the bond pads to thereby form bonds there between. A system for performing the above method is also disclosed.

Description

technical field [0001] The present invention generally relates to methods of packaging semiconductor components or devices. More specifically, the present invention relates to methods of making flip chip semiconductor packages. Background technique [0002] Semiconductor packaging generally involves encapsulating or housing a semiconductor component or device (eg, a semiconductor chip) within a device carrier or substrate. The device carrier or substrate supports the semiconductor chip and facilitates convenient handling of the semiconductor chip. Furthermore, the device carrier includes external connections or terminals for electrically connecting the semiconductor chip to external circuits. [0003] Known methods of semiconductor packaging, and more specifically, methods of forming flip chips on lead frame (FCOL) semiconductor packages, employ electroplated lead frames. A lead frame is a patterned sheet of metal. The metal sheet (usually copper) is usually plated with ...

AI Technical Summary

Problems solved by technology

[0009] However, the reduced pitch or distance between pads or electrical interconnects of semiconductor chips increases the risk and occurrence of bridging between adjacent pads or electrical interconnects, resulting in electrical shorts

[0010] Accordingly, the increased risk and occurrence of electrical shorts between adjacent pads or electrical connections adversely affects the reliability and quality of the fabricated semiconductor packages

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