Method for manufacturing semiconductor device structure

Abstract

The invention discloses a method for manufacturing a semiconductor device structure, which includes: providing a substrate with an ion trap, a gate structure corresponding to the ion trap formed above the substrate; and forming a gate structure on the periphery of the gate structure from outside to A first spacer structure containing a first sidewall layer structure, a first offset sidewall layer structure and a first pad oxygen layer structure in sequence; forming an epitaxial region on the substrate; removing the first spacer structure. A first sidewall layer structure; a lightly doped region is formed in the substrate inside the epitaxial region and immediately adjacent to the epitaxial region, and part of the lightly doped region is located below the first offset sidewall layer structure ; and forming a second sidewall layer structure outside the first offset sidewall layer structure, and forming a source / drain region in the substrate to obtain a semiconductor device structure. The above method can make the LDD region and the epitaxial region less overlap, and can reduce the epitaxial film loss of the gate structure that occurs when forming the first offset sidewall layer structure.

Description

technical field [0001] The invention relates to a semiconductor manufacturing process, in particular to a method for manufacturing a semiconductor device structure. Background technique [0002] With the increasing progress of semiconductor integrated circuit manufacturing technology, the gate size is getting smaller and smaller, and the conductive channel is getting shorter and shorter. The impact of the formed PN junction leakage current on the performance of the semiconductor device structure is also becoming more and more obvious. If the composition or structure of the semiconductor device is not changed, simply scaling down the semiconductor device will become unfeasible due to its excessive saturation leakage current (IDSS), so the semiconductor device will change some components while scaling down. Composition or structure to reduce IDSS. A typical semiconductor device structure may be a complementary metal oxide (CMOS) device structure. The CMOS device structure in...

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Problems solved by technology

[0005] However, the problem with the above process is that the LDD region and the epitaxial region in the prepared PMOS region often overlap

As a result, the epitaxial region and the LDD region are mutually restricted, resulting in a reduction in the strain effect of the epitaxial region, and at the same time making the LDD region unable to reduce the leakage current of the PN junction in the formed PMOS region and the potential actually applied to the depletion layer in the PMOS region , so that the power consumption of the semiconductor device structure cannot be reduced, and the semiconductor device structure that conforms to the actual process cannot be obtained

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