Integrated circuit device and manufacturing method thereof
A technology of integrated circuits and manufacturing methods, which is applied in the direction of circuits, semiconductor/solid-state device manufacturing, electrical components, etc., can solve problems such as the impact of bare chip yield, and achieve the effect of avoiding oxidation
Active Publication Date: 2011-12-14
TAIWAN SEMICON MFG CO LTD
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Problems solved by technology
Therefore, it adversely affects the yield of die-to-wafer bonding
Method used
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[0042] The manufacture and use of the examples are described below. It should be noted, however, that the embodiments provide many inventive concepts that can be widely applied. The specific embodiment is only used to illustrate the specific usage of the embodiment, but the present invention is not limited thereto.
[0043] The present invention provides novel bump structures and methods of forming them. Intermediate stages in the manufacture of an embodiment are illustrated, and different embodiments are discussed. In the various descriptions and drawings, like reference numerals refer to like elements.
[0044] refer to figure 1 , providing a workpiece 2 comprising a substrate 10 . The work piece 2 can be a device die including active components such as transistors; however, the work piece 2 can also be a package substrate or an interposer without active components therein. In one embodiment, the workpiece 2 is a bare device, and the substrate 10 may be a semiconductor...
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The present invention discloses an integrated circuit device and a manufacturing method thereof. A work piece includes a copper bump having a top surface and sidewalls. A protection layer is formed on the sidewalls, and not on the top surface, of the copper bump. The protection layer includes a compound of copper and a polymer, and is a dielectric layer. According to the integrated circuit device and the manufacturing method thereof, in a bonding technology of a bare chip to a chip, the protection layer also can avoid oxidation of the copper bump even if a temperature of the work piece is high.
Description
technical field [0001] The invention relates to an integrated circuit, in particular to a copper bump structure with a protective layer on the side wall. Background technique [0002] Die-to-wafer bonding is a common bonding method in which semiconductor die singulated from a wafer are bonded to semiconductor chips on the wafer that have not been singulated. With die-to-wafer bonding, a known good die can be selected for bonding to the wafer. Therefore, the yield is improved compared to wafer-to-wafer bonding. [0003] Traditional die-to-wafer bonding methods have disadvantages. A wafer may include many chips (hereinafter referred to as bottom chips), sometimes more than a thousand chips. Therefore, more than a thousand dies need to be bonded to the bottom chip one by one. During the entire bonding process, the wafer must be heated. However, the temperature of the wafer is difficult to control. If the temperature is too high, the copper bumps on the bottom chip will be...
Claims
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IPC IPC(8): H01L23/488H01L21/60
CPCH01L2224/13113H01L24/11H01L2224/13644H01L2224/13139H01L2924/01327H01L24/81H01L2224/13164H01L2224/81815H01L2224/92248H01L2224/81193H01L2224/13022H01L2224/13565H01L23/488H01L2224/13118H01L2224/13664H01L2224/73204H01L2224/94H01L2224/11823H01L24/13H01L24/16H01L2224/13083H01L2924/01322H01L2924/10253H01L2224/32225H01L2225/06513H01L2924/14H01L2224/13564H01L2224/13578H01L2224/13155H01L2225/06541H01L2224/13655H01L2224/13111H01L2224/05571H01L2924/37001H01L2224/1369H01L2224/16148H01L2224/13147H01L2224/13157H01L2224/97H01L2224/13144H01L2224/1357H01L2224/13583H01L2224/1182H01L2224/13017H01L2224/10126H01L2224/32145H01L2224/10145H01L25/0657H01L2224/05099H01L2224/05599H01L2924/0002H01L2224/0401H01L2224/16058H01L2924/00011H01L2924/00H01L2224/81H01L2224/16225H01L2924/00012H01L2224/16145H01L2924/00014H01L2924/01029H01L2924/01047H01L2224/05552H01L2224/81805H01L24/73H01L24/92H01L24/94H01L2224/92125H01L2224/1191H01L2224/81801H01L2924/014
Inventor 林俊成黄雅希陈新瑜蔡柏豪林彦甫黄震麟蔡方文邱文智
Owner TAIWAN SEMICON MFG CO LTD