Isolation area, semiconductor device and forming method thereof

Abstract

The invention discloses an isolation area, which comprises a first groove embedded in a semiconductor substrate and an insulating layer filled in the first groove, wherein the first groove comprises a first side wall, a bottom wall and a second side wall which extends from the bottom wall and is connected with the first side wall, and an included angle between the first side wall and a normal line of the semiconductor substrate is more than a standard value. A forming method of the isolation area comprises the steps of: forming the first groove on the semiconductor substrate, wherein the included angle between the first side wall of the first groove and a normal line of the semiconductor substrate is more than the standard value; forming a mask on the side wall and forming a second groove on the semiconductor substrate by using the mask; and forming an insulating layer to fill the first groove and the second groove. In a semiconductor device and a forming method thereof, a semiconductor substrate material is clamped between the second groove for bearing a semiconductor layer, which is used for formation of a source area and a drain area, and the first side wall and the second side wall. The isolating area and the semiconductor device in the invention are beneficial to decrease of electric leakage.

Description

technical field [0001] The present invention relates to the technical field of semiconductors, in particular to an isolation region, a semiconductor device and a forming method thereof. Background technique [0002] Currently, methods for forming semiconductor devices include: first, as figure 1 and figure 2 As shown, an active region 20 and an isolation region 12 surrounding the active region 20 are formed on a semiconductor substrate 10; subsequently, as image 3 and Figure 4 As shown, a gate stack structure is formed (the gate stack structure includes a gate dielectric layer 22, a gate 24 formed on the gate dielectric layer 22 and sidewalls 26 surrounding the gate dielectric layer 22 and the gate 24 , in practice, a capping layer is also formed on the gate, and the capping layer is usually silicon nitride, which can prevent the gate from being damaged during operation. For the convenience of description, the text and drawings in this document , the capping layer is ...

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Problems solved by technology

[0003] However, if Figure 7 to Figure 9 As shown, it is found in practice that a gap 34 is formed at the junction of the source-drain region 32 and the isolation region 12; then, as Figure 10 to Figure 12 As shown, when the contact region 36 (such as a metal silicide layer) is subsequently formed on the source and drain regions 32, the contact region 36 can easily pass through the gap 34 to reach the junction region, thereby causing leakage

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