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Characterization method for parasitical bipolar junction transistor of MOS (metal oxide semiconductor) transistor

A technology of MOS transistor and bipolar transistor, which is applied in the field of characteristic characterization of parasitic BJT, can solve the problems of complicated testing process, and achieve the effect of simplifying the testing process.

Active Publication Date: 2012-01-18
SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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  • Abstract
  • Description
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  • Application Information

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Problems solved by technology

However, when testing the base current, the testing device needs to be in contact with the body region 13, which makes the whole testing process more complicated.

Method used

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  • Characterization method for parasitical bipolar junction transistor of MOS (metal oxide semiconductor) transistor
  • Characterization method for parasitical bipolar junction transistor of MOS (metal oxide semiconductor) transistor
  • Characterization method for parasitical bipolar junction transistor of MOS (metal oxide semiconductor) transistor

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Embodiment Construction

[0020] The test method of the present invention calculates the current gain coefficient β of the parasitic bipolar transistor in the MOS transistor by measuring the gate-induced drain leakage current Igidl of the MOS transistor, thereby generating the current gain coefficient β and the source electrode and the drain electrode of the MOS transistor. The voltage Vds of the parasitic bipolar transistor, that is, the fitting function of the voltage Vce between the emitter and collector of the parasitic bipolar transistor, does not need to contact the body region of the MOS transistor. In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be further described in detail below in conjunction with the accompanying drawings.

[0021] see image 3 , image 3 is a flow chart of the testing method of the present invention. Preferably, the MOS transistor is a lateral SOI structure MOS transistor, and the parasitic bipo...

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Abstract

The invention relates to a characterization method for a parasitical bipolar junction transistor of a MOS (metal oxide semiconductor) transistor. The method comprises the following steps: measuring a leakage current Id of the MOS transistor; measuring a gate induced drain leakage current Igidl of the MOS transistor; measuring a voltage Vds between a source electrode and a drain electrode of the MOS transistor, namely a voltage Vce between an emitting electrode and a collecting electrode of the parasitical bipolar junction transistor; according to the measured leakage current Id and the measured gate induced drain leakage current Igidl, calculating a current gain coefficient beta of the parasitical bipolar junction transistor by using a formula: Id = (1+beta) Igidl; and generating a fit function of the current gain coefficient beta of the parasitical bipolar junction transistor and the voltage Vce between the emitting electrode and the collecting electrode of the parasitical bipolar junction transistor. By using the testing method disclosed by the invention, an operation of contacting a body area of the MOS transistor can be omitted, and the test process is simple.

Description

technical field [0001] The present invention relates to a characteristic characterization method of a parasitic bipolar transistor (Bipolar Junction Transistor, BJT) of a Metal Oxide Semiconductor (Metal Oxide Semiconductor, MOS) transistor, in particular to a silicon structure on a lateral (lateral) insulating substrate (Silicon On Insulator, SOI) MOS transistor parasitic BJT characteristic characterization method. Background technique [0002] MOS transistors with SOI structure are especially suitable for high-speed, low-voltage, and low-power circuits due to their advantages such as large current drive capability, steep sub-threshold slope, small short channel, and narrow channel effect. [0003] see figure 1 , figure 1 It is a schematic cross-sectional structure diagram of an SOI structure MOS transistor in the prior art. The transistor includes a supporting substrate 11, an insulating layer 12 formed on the surface of the substrate 11, a body region (body) 13, a sour...

Claims

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Application Information

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IPC IPC(8): G01R31/26
Inventor 余泳
Owner SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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